VHDL code for full subtractor & half subtractor using dataflow method – full code & explanation

The half subtractor and the full subtractor are combinational logic circuits that are used to subtract 2 1-bit number and 3 1-bit numbers respectively. They both produce two outputs, Difference and Borrow. The half subtractor does not account for any borrow that might take place in the subtraction. Hence, since it performs only half the operation, it is known as the half subtractor. The full subtractor, in contrast, has three inputs, one of which is the borrow input. Since the full subtractor considers the borrow operation it is known as a full subtractor. In this post, we will take a look at implementing the VHDL code for full subtractor & half subtractor. First, we will explain the logic and then the syntax. For the full code, scroll down.

Explanation of the VHDL code for full subtractor & half subtractor using dataflow method. How does the code work?

Since we will be coding the half subtractor and the full subtractor using the dataflow models, all we need is their logic equations.

Logic diagram and logic equation of the half subtractor

Half Subtractor

From the above logic diagram, the logic equations for the half subtractor are as follows

Difference =  A \oplus B

Borrow = A’B

Logic diagram and logic equation of the full subtractor

Full Subtractor

From the above logic diagram, the logic equations for the full subtractor are as follows

Difference = { A\oplus B\oplus D }

Borrow = A'(B+D) + BD

We can either code both the circuits using the same inputs or we can use separate inputs for them. We will proceed with the option of the same inputs. Hence we will first declare standard (non-vector) inputs using STD_LOGIC. We will, however, need separate outputs so as to not jumble up our results. This way we can get outputs for both the circuits. Both the circuits have two outputs, Difference and Borrow. Hence we will declare two Difference ports and two Borrow ports. Let’s declare them as vectors so that we will automatically get Difference 0 and Difference 1, and Borrow 0 and Borrow 1. The entity name is SUBTRACTOR_SOURCE.

[cc lang=”vhdl”]

Port ( A, B, C : in  STD_LOGIC;

DIFFERENCE, BORROW : out  STD_LOGIC_VECTOR (1 downto 0));

end SUBTRACTOR_SOURCE;

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Next, we will declare that the architecture we are using for this program is dataflow. And hence the single begin statement will follow the architecture statement.

[cc lang=”vhdl”]

architecture dataflow of SUBTRACTOR_SOURCE is

 

begin

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In the next lines of code, we will assign the output ports to the logic equations of the corresponding outputs we saw above. Vector 1 outputs belong to the half-subtractor and vector 0 outputs belong to the full-adder. This is arbitrary assignment though. It can be the other way around too. The important part is to assign the vector position (0 or 1) using brackets in front of the port names.

[cc lang=”vhdl”]

—half subtractor

 

DIFFERENCE(1) <= A xor B;

BORROW(1) <= (not A) and B;

 

—full subtractor

 

DIFFERENCE(0) <= A xor B xor C;

BORROW(0) <= ((not A) and (B or C)) or (B and C);

 

end dataflow;

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At the end of the program, the end dataflow command indicates that the program with the dataflow architecture is complete.

Full VHDL code for full subtractor & half subtractor using dataflow method

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;




entity SUBTRACTOR_SOURCE is

Port ( A, B, C : in  STD_LOGIC;

DIFFERENCE, BORROW : out  STD_LOGIC_VECTOR (1 downto 0));

end SUBTRACTOR_SOURCE;



architecture dataflow of SUBTRACTOR_SOURCE is


begin


---half subtractor


DIFFERENCE(1) <= A xor B;

BORROW(1) <= (not A) and B;


---full subtractor


DIFFERENCE(0) <= A xor B xor C;

BORROW(0) <= ((not A) and (B or C)) or (B and C);



end dataflow;

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