In this post, we will take a look at implementing the VHDL code for a multiplexer using behavioral method. Any digital circuit’s truth table gives an idea about its behavior. First, we will take a look at the truth table of the multiplexer and then the syntax. For the full code, scroll down.
Explanation of the VHDL code for multiplexer using behavioral method. How does the code work?
A multiplexer is a data selector. It has multiple inputs, out of which it selects one and connects it to the output. This selection is made based on the values of the select inputs.
In this program, we will write the VHDL code for a 4:1 Mux. A 4:1 mux will have two select inputs. Since we are using behavioral architecture, it is necessary to understand and implement the logic circuit’s truth table.
Truth table of a 4:1 Mux
The I/O ports of the multiplexer will be vector entities as we are going to code in the truth table. Let’s name our entity as
MUX_SOURCE and write the syntax for the entity-architecture pair. Note the two
begin statements with the
process statement in between as is customary with the behavioral architecture.
entity MUX_SOURCE is Port ( S : in STD_LOGIC_VECTOR (1 downto 0); I : in STD_LOGIC_VECTOR (3 downto 0); Y : out STD_LOGIC); end MUX_SOURCE; architecture Behavioral of MUX_SOURCE is begin process (S,I) begin
We will code the behavior of the circuit using the if-elsif statements that are available to us in the behavioral architecture. We have seen on multiple occasions in this VHDL course that the benefit of using the if-elsif statements versus the if-else statements is that you have to use only one closing statement for the entire command. So you can encode multiple
if statements and have to remember to use only one
end if statement at the end of the VHDL program. The syntax for coding in the truth table is shown below:
if (S <= "00") then Y <= I(0); elsif (S <= "01") then Y <= I(1); elsif (S <= "10") then Y <= I(2); else Y <= I(3);
Full VHDL code for multiplexer using behavioral method
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity MUX_SOURCE is Port ( S : in STD_LOGIC_VECTOR (1 downto 0); I : in STD_LOGIC_VECTOR (3 downto 0); Y : out STD_LOGIC); end MUX_SOURCE; architecture Behavioral of MUX_SOURCE is begin process (S,I) begin if (S <= "00") then Y <= I(0); elsif (S <= "01") then Y <= I(1); elsif (S <= "10") then Y <= I(2); else Y <= I(3); end if; end process; end Behavioral;
Testbench waveform for 4:1 Mux
Were you able to encode your multiplexer? Let us know what you did differently by commenting below. Also, would you like us to include the VHDL code for an 8:1 mux?