VHDL code for multiplexer using behavioral method – full code and explanation

In this post, we will take a look at implementing the VHDL code for multiplexer using behavioral method. Any digital circuit’s truth table gives an idea about its behavior. First, we will take a look at the truth table of the multiplexer and then the syntax. For the full code, scroll down.

Explanation of the VHDL code for multiplexer using behavioral method. How does the code work?

A multiplexer is a data selector. It has multiple inputs, out of which it selects one and connects that one to the output. This selection is done on the basis of the values of the select inputs. In this program, we will write the VHDL code for a 4:1 Mux. A 4:1 mux will have two select inputs. Since we are using behavioral architecture, it is necessary to understand and implement the logic circuit’s truth table.

Truth table of a 4:1 Mux

I0 I1 I2 I3 S0 S1 Y
I0 x x x 0 0 I0
x I1 x x 0 1 I1
x x I2 x 1 0 I2
x x x I3 1 1 I3

The I/O ports of the multiplexer will be vector entities as we are going to basically code in the truth table. Let’s name our entity as MUX_SOURCE and write the syntax for the entity-architecture pair. Note the two begin statements with the process statement in between as is customary with the behavioral architecture.

entity MUX_SOURCE is

    Port ( S : in  STD_LOGIC_VECTOR (1 downto 0);

           I : in  STD_LOGIC_VECTOR (3 downto 0);

           Y : out STD_LOGIC);

end MUX_SOURCE;


architecture Behavioral of MUX_SOURCE is


begin


process (S,I)


begin

We will code the behavior of the circuit using the if-elsif statements that are available to us in the behavioral architecture. A benefit of using the if-elsif statements versus the if-else statements is that you have o use only one closing statement for the entire command. So you can encode multiple if statements and have to remember to use only one end if statement at the end of the VHDL program. The syntax for coding in the truth table is shown below.

if (S <= "00") then

Y <= I(0);

elsif (S <= "01") then

Y <= I(1);

elsif (S <= "10") then

Y <= I(2);

else

Y <= I(3);

 

Full VHDL code for multiplexer using behavioral method

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity MUX_SOURCE is

    Port ( S : in  STD_LOGIC_VECTOR (1 downto 0);

           I : in  STD_LOGIC_VECTOR (3 downto 0);

           Y : out STD_LOGIC);

end MUX_SOURCE;


architecture Behavioral of MUX_SOURCE is


begin


process (S,I)


begin


if (S <= "00") then

Y <= I(0);

elsif (S <= "01") then

Y <= I(1);

elsif (S <= "10") then

Y <= I(2);

else

Y <= I(3);


end if;


end process;


end Behavioral;

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