The ability to store data in something we made out of silicon is just mind-boggling to me. It is like flying airplanes. Sure you will read about how it works and you will understand the physics behind it. But when you are sitting in a flight, tied to a chair hurtling through the sky in a metal box, all the science goes right out the window and the feat is just impressive. Quite similarly storing of memory is a very important technology. This is possible due to semiconductors. And we have the ability to store digital data due to flip-flops and latches.

Starting off, we will first see what latches are. Then we will what flip-flops are. And then compare them with latches. Finally, we will see the different types of flip-flops and understand their working. We will also tabulate the truth tables of all flip-flops.

**What is a digital latch?**

A digital latch is the building block of sequential circuits. It is made using NOR or NAND logic gates. Latches have a feedback system. This means that the output of the latch is given back to its input. This indicates that the outputs of a latch depend on current as well as previous inputs. A latch has two inputs and two outputs. The outputs are complementary to each other.

A latch has two stable state outputs. This means that there are two cases of inputs where the output of a latch is stable. This is why it is also known as a bistable multivibrator. The latch keeps shifting between these two states whenever there is a change in the input signal. The two stable states are known as SET and RESET states.

Further along, we will look at how latches make up flip-flops. However, flip-flops are synchronous devices because they have clocks. Latches, on the other hand, are asynchronous devices.

**What are the types of latches?**

Depending on the types of logic gates we classify the digital latches into two main types. The SR NAND latch and the SR NOR latch. We have Their function is similar, however, their truth tables are opposite of each other.

**SR Latch using NAND gate**

The construction is simple. Two inputs, S and R. Two outputs that are complementary to each other, Q and Q’. And the outputs are fed back to the gates. The SR latch truth table and working of the SR latch are given below.

**Case 1**

For the input S=1; R=0 the output of the lower NAND gate is 1. Because from the NAND truth table, even one low input gives you a high output. Thus Q’=1. The input to the upper NAND gate is now 1 NAND 1, which is equal to 0. Q =0. Thus, the outputs satisfy their complementary relationship. In this case, the latch is said to be in the RESET state.

**Case 2**

For the input S=0; R=1 the output of the upper NAND gate is 1. Thus Q=1. The input to the lower NAND gate is now 1 NAND 1, which is equal to 0. Q’ =0. Thus, the outputs satisfy their complementary relationship. In this case, the latch is said to be in the SET state.

**Case 3**

When the inputs are S=1; R=1 the output of the upper NAND gate is (1.Q’)’. That is using the NAND logic equation. (1.Q’)’ = Q. Similarly, the output of the lower NAND gate is (1.Q)’ = Q’. Thus the two outputs are Q and Q’. Hence we can say that for this input combination, the SR NAND latch gives the previous outputs as the new outputs. Which basically shows that the latch held on to the previous outputs. This is how a latch acts as a memory cell.

**Case 4**

When the inputs are both 0, the outputs of both the NAND gates are 1. This is not right because the outputs are supposed to be complementary to each other. Thus this particular input configuration is not allowed.

**SR NAND latch t****ruth table**

S |
R |
Q |
Q’ |

0 | 0 | No change | No change |

0 | 1 | 1 | 0 |

1 | 0 | 0 | 1 |

1 | 1 | Not allowed | Not allowed |

**SR Latch using NOR gate**

The SR latch using the NOR logic gate is quite similar in construction and working to the SR NAND latch. There are a few difference though. This latch, due to the difference in the logic of NAND and NOR, SETS at S=1; R=0 and resets at S=0; R=1. Another main difference that the output of the first NOR gate is Q’ and not Q. The outputs interchange their positions in an SR NOR latch. This version of the SR latch’s truth table is given below.

**SR NOR latch truth table**

S |
R |
Q |
Q’ |

0 | 0 | No change | No change |

0 | 1 | 0 | 1 |

1 | 0 | 1 | 0 |

1 | 1 | Not allowed | Not allowed |

**What are flip-flops?**

Flip-flops are also the building blocks of sequential circuits. They are made using latches. They are circuits where the output depends not only on the current input but also on the previous inputs. They are also known as memory cells as they can store one bit of binary data. In fact, flip-flops are the fundamental memory units in electronics. Flip-flops work on the application of a clock signal. This makes them synchronous. A flip-flop has two inputs and two outputs. The outputs (Q and Q’) are complements of each other.

Like a latch, a flip-flop is a bistable multivibrator too. It has two stable states. When Q = 1; Q’ = 0, the flip is said to be in a set state. When Q = 0;Q’ = 1, it is said to be in a reset state. Basic digital circuits like shift registers and counters are made using flip-flops. So are complex devices like FPGAs, CPLDs, and RAMs.

**What are the different types of flip-flops?**

We have four main types of flip-flops.

- SR flip-flop (Set-Reset flip-flop)
- D flip-flop (Delay/Data flip-flop)
- T flip-flop (Toggle flip-flop)
- JK flip-flop (Jack-Kilby flip-flop)

Apart from these main versions, there are a few modified versions as well. We will be looking at one of those in particular.

- Master-Slave JK flip-flop

**What are the differences between latches and flip-flops?**

Latches |
Flip-Flops |

latches are built using gates | flip-flops can be made using latches |

latches don’t have a clock input | flip flops have a clock input |

latches change output as soon as there is a change in input. This means that they are asynchronous. | flip flops change output at the edge of a clock pulse. Flip-flops are synchronous. |

latches are level-triggered | flip-flops are edge-triggered |

Latches are naturally faster because they don’t have a clock. | Flip-flops are slower |

Since they don’t have a clock, there is no need to carefully route any clock signals. Hence the design is simpler | When dealing with clock signals, you need to make sure that all the modules receiving the clock signal get it without a delay. Hence the routing of the clock needs to be smart and effective. This makes the design of flip-flops a bit more complex. |

Low power consumption | High power consumption |

**How to design an SR Flip Flop?**

An SR flip-flop is an extension of the SR latch. So let’s take our SR latch (NAND gates). Attach the outputs of two new NAND gates to the inputs of the SR latch. Apply a common clock input to the new NAND gates. The other inputs to the first and second new NAND gates are S and R respectively. This is how we construct an SR flip-flop. We will finally, at the end of this working, tabulate the SR flip-flop truth table too.

**Working of an SR flip-flop/SR flip-flop truth table explanation**

As we know, flip-flops are edge-triggered devices. Which means that a clock input is necessary to enable them. More specifically, flip-flops take in or consider new inputs only at the edge of a clock pulse. This clock pulse can either be rising or falling. Let’s start with plotting the truth table for various cases of inputs. Since we are using NAND gates, you might want to pull up this truth table of a NAND gate in a new tab to refer. Just in case you don’t remember it by heart.

**CLOCK = 0; S, R = x**

In the first case, we will apply no clock and see what happens. Refer the logic diagram above. When no clock is given to the NAND gates, their outputs will have the logic 1. This is because, if you refer to the NAND gate’s truth table, for even a single low input, the output is high. So the outputs of the two NAND (A and B) gates are 1 regardless of the S and R inputs. These two outputs act as inputs to the next two NAND gates. Let’s call the top gate with output Q as gate x and the lower gate with Q’ output as gate y. Gate x has gate y’s output as input. Likewise, gate y has gate x’s output as input. Hence since they are NAND gates, we know Y = (A.B)’

Q = (1.Q’)’ and Q’ = (1.Q)’

Now there are two possible values for both Q and Q’. 0 and 1. Let’s put those two values in the above equations and see what we get.

**Case 1**: When Q = 1; Q’ = 0

Q = (1.0)’ = 1 and Q’ = 0. This means that the flip-flop is retaining it’s values. Hence, it is acting as a memory holding device.

**Case 2**: When Q = 0; Q’ = 1

Putting in the equations above

Q = (1.1)’ = 0 and Q’ = 1. In this case too, the flip-flop is retaining its previous values.

Hence as a whole, we can say that when the clock input is 0, the SR flip-flop is switched OFF and the **SR flip-flop retains its previous values and acts as a memory holding device. **

Now let’s move on and provide a clock input to the SR flip-flop to actually get it started.

**CLOCK = 1; S, R = 0**

Let the S and R inputs be 0. In the previous case, the clock input was 0 and the outputs of the gates A and B was 1. This case is quite similar. S and R are 0, the clock is 1. Thus the outputs of both the NAND gates will be 1 and the same scenario as above will repeat itself. Hence we can say that when the clock is high and the inputs to the SR flip-flop are 0, the SR flip-flop retains its previous values and acts as a memory device.

**CLOCK = 1; S = 0, R = 1**

In this case, the output of gate A will be 1 (refer to NAND truth table, any one low output means output is high). The output of gate B will be 0 as both inputs are 1. Hence the outputs of gate X and gate Y are shown below respectively.

Q = (1.Q’)’ and

Q’ = (0.Q)’ = this is always going to be 1 because of the 0 input.

Hence

Q = (1.1)’ = 0

Thus for S = 0; R = 1, outputs are Q = 0; Q’ = 1. Hence, we can say that there is a change of state in this configuration. This is one of the two stable states of the SR flip-flop.

**CLOCK = 1; S = 1, R = 0**

Alright so now you should be able to do this by yourself. Try it out. It’s an important skill to have as we progress to understand other flip-flops.

The output of gate A will be 0 as S and clock are both high. The output of gate B will be 1 as R is 0. Thus we will get the following equations for the outputs of gates X and Y.

Q = (0.Q’)’ = 1

Q’ = (1.Q)’ = 0

Thus for S = 1; R = 0 we get Q = 1 and Q’ = 0. Hence, we can say that there is a change of state in this configuration. This is the second and final of the two stable states of the SR flip-flop.

**CLOCK = 1; S = 1, R = 1**

The output of both the gates, A and B will be 0. Thus the output of both the gates X and Y will be 1. This is not possible and hence this configuration is not allowed. Now we can summarize these in a truth table.

**SR flip-flop truth table**

CLK |
S |
R |
Q |
Q’ |

0 | x | x | Qprv | Q’prv |

1 | 0 | 0 | Qprv | Q’prv |

1 | 0 | 1 | 0 | 1 |

1 | 1 | 0 | 1 | 0 |

1 | 1 | 1 | – | – |

**What’s the JK Flip Flop circuit design like?**

We can design a JK flip-flop circuit using an SR flip-flop. This construction can be done by attaching two AND gates to the inputs of the SR flip-flop. The inputs to these AND gates are the cross-coupled outputs from the SR flip-flop (Q and Q’). And the J and K inputs.

From this diagram of the JK flip-flop circuit, we can deduce that

S = J.Q’

R = K.Q

**Working of a JK flip-flop circuit**

Earlier we saw that flip-flops deal with the present and past values to give an output. So far into our study of flip-flops, we have conveniently not dealt with the past inputs because we are able to get by using simple NAND gate logic. Like, in the SR flip-flop, we could predict the values of Q or Q’ depending on which NAND gate had a 0 input. Because then that gate’s output (Q or Q’) would be 1. So yeah, we were able to put off dealing with past inputs.

But now, we will have to account for past outputs to understand JK flip-flops. Don’t be afraid though, we will break it down into small bite-size cases. (techno*byte*, get it? Sorry bad pun).

**Case 1**

Let’s take the input case of when J=1; K=0. Since we are considering previous outputs, we have two possible cases. One when the previous Q was 0, two, when the previous Q was 1. Let’s consider both cases. Keep scrolling to the truth table below to understand what’s going on. We got two equations above from the construction of the JK flip-flop. Let’s get those two down here.

S = J.Q’

R = K.Q

Using this, we will calculate the values of the SR flip-flop inputs to be recorded in the next column. For the first case of previous outputs,

S = J.Qprv’ = 1.0 = 0

R = K.Qprv = 0.0 = 0

So SR = 0 for Q=1; Q'(previous) = 0. Similarly, for Q=0; Q'(prv) = 1, SR = 10.

Now consider the SR and QQ'(current) columns. From the truth table of the SR flip-flop, when the inputs are 00, the new(in our case, current) outputs are the same as the previous outputs. Hence QQ'(current) = QQ'(previous) = 10.

Now for SR = 10, QQ'(current) will be equal to 10, from the truth table for the SR flip-flop.

What we can see is that for all possible cases of previous inputs, when the input to a JK flip-flop is 10 (J=1; K=0), the output will always be Q=1; Q’=0.

CLK |
J |
K |
Qprv |
Qprv’ |
S |
R |
Qcurrent |
Qcurrent’ |

1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |

1 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 |

**Case 2**

When J=0; K=1. We have both the previous output cases in the table below. Let’s proceed with the first one Q=1; Q'(prv) = 0. From the equations of S and R above,

S = J.Qprv’ = 0.0 = 0

R = K.Qprv = 1.1 = 1

we get SR = 01. From SR flip-flop’s truth table, this gives an output of Q=0; Q'(current) = 1.

Similarly for Qprv=0; Qprv’=1, SR=00. Which indicates that there will be no change in the output. Hence, Qcurrent=0; Qcurrent’=1.

We can say that for all possible cases of previous inputs, when the input to a JK flip-flop is 01 (J=0; K=1), the output will always be Q=0; Q’=1.

CLK |
J |
K |
Qprv |
Qprv’ |
S |
R |
Qcurrent |
Qcurrent’ |

1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 1 |

1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 |

**Case 3**

In this case, we will give no input to the JK flip-flop. That is, J=0; K=0. For the first case of the previous output, Qprv=1; Qprv’=0, we get SR = 00 by using the equations derived above. This indicates that there won’t be any change in the output. Hence Qcurrent remains same as Qprv.

For Qprv=0; Qprv’=1, again SR=00. Hence, in this case too, Qcurrent = Qprv.

Thus we can say that for an input of 00, a JK flip-flop holds its previous output and acts as a memory cell. Thus for JK=00; Qcurrent=Qprv.

CLK |
J |
K |
Qprv |
Qprv’ |
S |
R |
Qcurrent |
Qcurrent’ |

1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 |

1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 |

**Case 4**

In this last case, J=1; K=1. For the first case Qprv=1; Qprv’=0, we get SR = 01 by using the equations we have for S and R from the construction of the JK flip-flop. Thus the output for SR=01 is Qcurrent=0; Qcurrent’=1.

For Qprv=0; Qprv’=1, SR=10. Qcurrent=1; Qcurrent’=0.

If you notice closely, the current outputs are opposite to that of the previous outputs. Hence we can say that for an input of 11, a JK flip-flop toggles its previous output. Thus, for JK=00; Qcurrent=Qprv’.

CLK |
J |
K |
Qprv |
Qprv’ |
S |
R |
Qcurrent |
Qcurrent’ |

1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 1 |

1 | 1 | 1 | 0 | 1 | 1 | 0 | 1 | 0 |

**Truth table for JK flip-flop**

We can summarize the above cases into this easy to remember truth table.

CLK |
J |
K |
Q |
Q’ |

1 | 0 | 0 | Qprv | Qprv’ |

1 | 0 | 1 | 0 | 1 |

1 | 1 | 0 | 1 | 0 |

1 | 1 | 1 | Qprv’ | Qprv |

**Advantage and disadvantage of JK flip-flop**

- The advantage of a JK flip-flop is that it removes the not allowed condition present in the SR flip-flop for an input of SR=11. In JK flip-flop, an input of 11, gives a toggle output.
- The disadvantage is that something known as a
is created in the JK flip-flop. This condition presents itself at JK = 11 input. As we know that the flip-flop toggles the previous output in this configuration. However, the problem is that it does not stop toggling. For every clock pulse, the output keeps toggling. Hence to avoid the race-around condition of the traditional JK flip-flop, we upgrade it to a Master-Slave configuration to remove this disadvantage.*race-around condition*

**How to design a Master-Slave JK flip-flop?**

The construction is simple if you can notice a tiny detail. The circuit, if cut in half, is actually an extension of itself, albeit with a complemented clock input to the second half. Here’s another trick, make two SR flip-flops, with the output of the first as an input to the second. Connect a common clock input, just attach a NOT gate to it before connecting it to the second SR flip-flop. Take the outputs of the second SR flip-flop and give that as a feedback input to the first SR flip-flop. The first SR flip-flop is the Master and the second SR flip-flop is the slave in this configuration. This is because the second one activates after the first one does. And in doing so, it is “following” the Master. We’ll now explain the working of a master-slave JK flip-flop below.

**Working of a Master-Slave JK flip-flop**

The second half of the circuit which has the inverted clock input works as a flip-flop only when the clock is low. When the clock is high (i.e 0 for this second half), the second half gives its previous output as its current output. Why? Because, as we have seen earlier with the SR flip-flop, a clock input of 0 makes it work like a memory cell and give its previous output. So this unchanged output is given as feedback input to the Master.

Now when the inputs to this flip-flop are both 1. That is, J=1; K=1, the output won’t keep toggling. Because the slave is still inactive as a flip-flop and giving its previous value as the output. Therefore, in this way, the race around condition is eliminated. The incessant toggling is taken care of in this design.

**Master-Slave JK flip-flop truth table**

The truth table of the Master-Slave JK flip-flop is the same as that of the traditional JK flip-flop. There are only two changes.

- The Master-Slave JK flip-flop is a negative edge triggered flip-flop. So instead of CLK=1 in the JK flip-flop’s truth table, you should write 0.
- Now the output won’t toggle uncontrollably at J=1; K=1 input.

**How to design a D Flip-Flop?**

A D flip-flop stands for a data or delay flip-flop. The outputs of this flip-flop are equal to the inputs. We can make a D flip-flop using both SR and JK flip-flops. The construction is similar. Only one input is given to the flip-flop. The other input is the invert of the input given. We achieve the inversion using a NOT gate. Now, it is a data or delay flip-flop depending on whether the SR/JK flip-flop requires positive or negative edge triggering respectively.

If the situation demands it, we can also construct a D flip-flop with an enable pin by using an AND gate.

**Working of a D flip-flop**

Regardless of the type of flip-flop, we use to make the D flip-flop. The input to the second port will always be inverse to the input of the first port. If we observe the truth tables of SR and JK flip-flop, the outputs for the cases where are the same. That is how we get the following truth table for the D flip-flop.

### Truth table for D flip-flop

CLK |
D |
Q |
Q’ |

0 | x | No change | No change |

1 | 0 | 0 | 1 |

1 | 1 | 1 | 0 |

**How to design a T Flip-Flop?**

The T in T flip-flop stands for toggle. This implies that the output will change from the previous value with a change in the input. We can construct a T flip-flop using a JK flip-flop.

**Working of a T flip-flop**

When 0 is given at the input T, we get the output equivalent to the 00 input of the JK flip-flop. Which is, no change. This means that at an input of 0, the T flip-flop shows whatever the value was present at the output earlier. It could be 0 or 1.

When 1 is given at the input T, we get the output equivalent to the 11 input of the JK flip-flop. That is, toggle. This means that at an input of 1, the T flip-flop inverts whatever the previous value was present at the output earlier. It could be 0 or 1.

**Truth table for T flip-flop**

CLK |
T |
Q |
Q’ |

0 | x | No change | No change |

1 | 0 | Qprv | Qprv’ |

1 | 1 | Qprv’ | Qprv |

**An implementation of the T flip-flop truth table that shows the meaning of toggle output**

CLK |
T |
Q |
Q’ |

1 | 0 | 0 | 1 |

1 | 1 | 1 | 0 |

1 | 0 | 1 | 0 |

1 | 1 | 0 | 1 |

Toggle means to switch from whatever the last value was. The T flip-flop toggles at an input of 1. So if the previous output was 0, it toggles to 1 at an input of 1. If the previous output was 1, it toggles to 0 at an input of 1. And when 0 is the input, it shows no change in the output that was available previously.