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Data Transfer Techniques in 8085

A microprocessor is not used merely for running simple arithmetic operations or logical functionality. It also performs many Input-Output actions, data transfer functions, and a lot more!

Why is Data Transfer needed?

We can connect several I/O devices and memory peripherals to a microprocessor. However, since different technologies are involved, there will be differences in the speed of operation and of data transfer.

Usually, when memory is connected with the microprocessor, there isn’t a stark difference in the processing speed since semiconductor memories are generally easily compatible with microprocessors. However, this might not always be the case.

But the problem often arises when external peripherals are connected as I/O devices. A slow I/O device won’t be able to transfer data at a satisfactory rate whenever the microprocessor requests for data transfer. And usually, the peripheral devices do have slower transfer rates than the processor. Maybe the processor might send two units of information per second, but the external device might only accept 1 unit of information per second. Or conversely, perhaps the external device expects quicker transfers, but our microprocessor might be sending information a bit slower.

This might lead to severe data losses, or the devices might get damaged, or there might even be chances for the system to slow down all over, thus affecting the overall efficiency of the system.

To avoid this problem, a number of data transfer techniques have been devised.

Since constant communication is required between the external device and the processor, these data transfer techniques play a crucial role in the efficient functioning of the system with the externally connected devices.

Classification of Data Transfer Schemes

We can broadly classify the data transfer schemes into two modes – Serial Data Transfer and Parallel Data Transfer.

data transfer techniques in 8085 table
Classification of the data transfer techniques in 8085

Our device, the Intel 8085 Microprocessor, is a parallel device. Thus, it transfers 8 bits of information simultaneously over 8 data lines in the parallel I/O mode. But sometimes, there are instances where using this data transfer technique might be just theoretical or impossible to apply. Using parallel data transfer can be expensive if communication is to take place over vast distances. Also, if the device, on the other hand, follows the protocol of serial communication only, then it is impossible to use parallel mode.

Difference between Parallel Data Transfer and Serial Data Transfer

As discussed earlier, we can broadly classify data transfer schemes into parallel data transfer techniques and serial data transfer techniques. Let us understand the differences between them.

Under this scheme, the data is transferred one bit at a time. Under this scheme, the data is transferred several bits at the same time.
It is a slower mode of data transfer. Data is transferred much quicker.
Serial data transfer is preferred when data is to be sent over a long distance and the cost of cables would be too expensive. Parallel data transfer is the preferred technique for short-distance communication.
For this mode, the transmitter first performs parallel – to – serial conversion and the serial – to – parallel conversion at the receiver. No such conversions are required at both the transmission and reception endpoints.
This mode requires a single line to transfer information. This mode requires multiple lines for data transfer.
Noise and errors are much lesser. As multiple bits are transmitted at the same time, there is scope for more error and noise.
Cables used for serial communication are much thinner, longer, and very economical. Here, the cables are much shorter, and thicker compared to the Serial communication cables.
This is a very reliable, inexpensive, and straightforward process. It is considered a little unreliable, expensive, and complicated process.

Parallel Data Transfer Techniques

We know that under the parallel data transfer scheme, multiple data bits can be transmitted at the same time. Thus, for the Intel 8085, 8 bits of data are sent all together using eight parallel lines. Let us go through the different types of parallel data transfer schemes. We have:

  • Programmed I/O Data Transfer
  • Interrupt Driven I/O Data Transfer
  • Device or Direct Memory Access (DMA) Data Transfer

Let us study each of these transfer schemes in detail.

Programmed I/O Data Transfer

  • This is a straightforward scheme under parallel data transfer mechanisms. This mode is generally preferred for simple, small microprocessor systems where speed is critical.
  • This method can work under the synchronous and asynchronous mode, depending on the speed and architecture of the I/O devices.
  • We also prefer this method when there is a small amount of information to be exchanged between the microprocessor and other devices that are placed near to the microprocessor. Example: Computer, printer, etc.
  • Using the IN and OUT instructions, data transfer is carried out between the microprocessor and I/O devices.
  • The processor reads the data from an input port or input device using the IN command.  The processor sends data out from the CPU to the output port or the output device using the OUT instruction.
  • Thus, as the speeds of the processor and external device match, the data transferring process is carried out using the IN and OUT instructions.

Synchronous Data Transfer Method

  • The word ‘Synchronous‘ means ‘taking place at the same time.’
  • Thus, to establish communication between our processor and the device, we need to set a common clock pulse. This common pulse synchronizes the peripheral device with the 8085 microprocessor.
  • This method is used when the speed of the microprocessor, Intel 8085, in this case, and the external peripheral device match with each other.
  • If the device is ready to send data, it can indicate via the READY pin of 8085.  Once the speeds match, the data transfer immediately begins, once a signal is issued by the microprocessor to begin transferring. The microprocessor need not wait for an extended period because of the matching speeds.
  • This technique of data transfer is seldom used to communicate with I/O devices though. Because I/O devices compatible with the microprocessor’s speed are usually not found.
  • Hence, this method of data transfer is most commonly employed for communicating with compatible memory devices.

Asynchronous Data Transfer Method

  • When the speed of the I/O device is slower than that of the microprocessor, we prefer the Asynchronous Data Transfer Method. As the speeds of both the devices differ, the I/O device’s internal timing is entirely independent of the microprocessor.
  • Thus, they are termed to be ‘asynchronous‘ from each other. The term asynchronous means ‘at irregular intervals.’

We implement the Asynchronous Data Transfer Method using the handshaking policy. But how is this method applied? And what happens next?

Under the handshaking method, the microprocessor and I/O device exchange a few signals before beginning the transfer of data between them.

Handshaking Protocol
Handshaking Protocol

Let us understand the flowchart of the handshake protocol.

  • First, the microprocessor raises a ready signal and sends it to the I/O device, which is connected to it.
  • The status of the I/O device is continually checked to see it is prepared for data transferring.
  • If the device is not ready, it is checked again and again until the device signals it is ready.
  • Once the device is ready, the data transfer begins from the microprocessor to the I/O device.

But how does the I/O device inform the microprocessor that it is ready for data transfer? This is done by the ‘ACK’ (Acknowledge) Signal. Also known as the handshake signal.

The microprocessor first checks the readiness of the I/O device continually. Once the I/O device is ready to accept data from the microprocessor, it sends an ACK signal to the microprocessor. This indicates the microprocessor that the device is all set for the reception of data. Now the data transmission can finally take place.

What happens if the opposite is supposed to happen? What if the I/O device has to submit information to the microprocessor?

In such a situation, the I/O device issues the ready signal back to 8085, informing it that it is ready to send data to the processor. In response to this ready signal, a valid data signal is sent by the 8085 to the I/O device, and then the valid information is put on the common data bus for the data transfer.

We can conclude by saying that under the Programmed I/O Data Transfer method, the microprocessor is always busy checking the status of the slower I/O device continuously for sharing data. Thus, some amount of time is wasted on the microprocessor’s behalf. Additionally, this method of data transfer is used by I/O devices and slow external memory peripherals.

Interrupt Driven I/O Data Transfer

The Programmed I/O Data Transfer, unfortunately, wastes a lot of time. Thus, the Interrupt Driven I/O Data Transfer is a much better option. Here, no extra time of the microprocessor is wasted in waiting for a response/signal from the external device. Under this method, the I/O device informs the microprocessor about its readiness, only when it is ready. This is accomplished by interrupting the Intel 8085.

  • To begin with, the microprocessor initiates the transfer of data by sending a request to the external device to be ‘get ready.’
  • Following this, the processor continues working normally, executing the original program rather than wasting its cycles by keeping a check on the status of the external I/O device.
  • Once the I/O device is all set to transfer information, it sends a control signal to the 8085 to inform its readiness. This control signal is called the Interrupt (INTR) signal.
  • Once the INTR signal is received by 8085, it responds to it by submitting an INTR acknowledgment signal back to the external I/O device.
  • When the I/O device gets the acknowledgment, both the devices are now prepared for the data transfer. The microprocessor completes the execution of the current instruction, then suspends the job. It saves all the contents and the status of the PC (Program Counter) into the stack memory and then proceeds with the subroutine program.
  • This subroutine program for the raised interrupt is called the Interrupt Service Subroutine (ISR) program.
  • This ISR first saves the status of our processor into the stack.
  • Once the data transfer is completed by executing the necessary instructions, the ISR restores the previous processor status and continues with the normal execution of the main program.

There may be different types of interrupt requesting configurations that might arise when the I/O devices are interfaced with the Intel 8085. They are :

  1. Single Interrupt System
  2. Multi Interrupt System

Single Interrupt System

Under the Single Interrupt System, only one interrupt wire/line is available with the processor to which multiple I/O devices are to be connected to.

Multiple Interrupt System

  • If the microprocessor has multiple interrupt terminals and to each interrupt terminal, one I/O device is to be connected, it is known as the multiple interrupt system.
  • Here, the total number of external devices to be linked with the interrupt wires/lines should be either equal to or lesser than the total number of interrupt terminals. Thus, one device is connected at a time to each level of the interrupt.
  • When a device interrupts the microprocessor, the processor immediately recognizes which device has raised the interrupt signal and identifies the location in the memory where the required subroutine is stored. This kind of interrupt scheme is referred to as a Vectored Interrupt.

Device or Direct Memory Access (DMA) Data Transfer

In the two schemes discussed earlier, the transfer of information between the I/O device and the mass storage device/memory is via the Accumulator register. But if there is a bulk amount of data to be transferred between the I/O device and the microprocessor, then these methods are unworthy of the investment being put into them, and even time – consuming.

To overcome such circumstances, the Direct Memory Access Data Transfer is put into use. This is an ideal method used for data transfer of a considerable amount between the microprocessor and the I/O device. It is also considered the fastest data transfer scheme.

But what makes it different from the previous two methods?

In the DMA scheme, the data is transferred between the I/O device (or DMA controller, a special IC) and the external memory directly without having any interference by the accumulator register. The processor gives up its control over the address bus as well as the data bus to the I/O device or DMA controller, thus aiding the exchange of information between the source and the destination directly.

We will now understand the working principle of the Direct Memory Access Data Transfer method.

Direct Memory Access Data Transfer
Direct Memory Access Data Transfer
  • First of all, we need to inform the microprocessor before beginning the process. For this, an I/O device first sends a request to a DMA controller using the DMARQ signal, which in turn forwards it to the processor in the form of a HOLD signal.
  • Once such a request is received by the microprocessor, it ceases its control over the address bus and data bus. It then informs the DMA Controller of the situation by sending an acknowledgment signal using the HLDA command.
  • The controller then informs the external peripheral by sending a DMACK signal.
  • The DMA controller then gains control over the two buses and monitors the transfer of information between the two locations (Memory and I/O).
  • Once the entire data transfer between the I/O device and the external memory gets over, the DMA Controller withdraws its request for using the data and address bus by disabling the HOLD and DMACK signals, and thus the microprocessor gains control over them again.

There are three types of techniques under the Direct Memory Access Data Transfer:

  1. Burst or block transfer DMA
  2. Cycle steal or the single-byte transfer DMA
  3. Transparent or hidden DMA

Burst or Block Transfer DMA

  • This is the fastest DMA mode of data transfer.
  • In the Burst mode, at least two or more bytes of data are transferred continuously i.e., the entire block of data is transferred in a straight sequence. Here, the microprocessor is disconnected from the main system during the data transfer, and thus, the processor is unable to execute any program on its own during the information transfer.
  • In fact, in this mode, the DMA controller acts as a Master.
  • If there are about N number of bytes to be transferred, then N number of machine cycles will be adopted into the working of the processor.
  • The DMA controller first sends a HOLD signal to the microprocessor to request access for the system’s buses, and in turn, wait for the HLDA signal.
  • One the HLDA signal is received, the DMA controller gets access over the system bus and sends one byte of information.
  • Once a single byte is sent, the memory address is incremented, the counter is decremented, and then the next byte is sent.
  • Thus, following this technique, all data bytes are transferred between memory and I/O devices. Once all the information is sent, the DMA controller disables the HOLD signal.
  • It then enters into the slave mode.
  • This method is generally used for loading data files or important programs into the memory. However, it keeps the CPU inactive for relatively long periods.

Cycle steal or Single-Byte transfer DMA

  • In this mode, only a single byte is transferred at a time.
  • This is thus much slower than burst DMA.
  • In the cycle-steal DMA, The DMA controller sends a HOLD signal to the microprocessor.
  • It then waits for the HLDA signal in return.
  • Once the HLDA signal is received, it gets access over the system buses and executes one DMA cycle only.
  • After this transfer, the HOLD signal is disabled, and it enters into the slave mode.
  • The processor thus gets back its control over the address and data bus and continues executing the following machine cycle.
  • However, if the counter has not touched down to zero, and there is still data to be exchanged, then the DMA controller sends a HOLD signal again to the processor, and sends the next byte of the information block.

Thus, only one DMA cycle takes place between every two machine cycles of the processor, and the execution speed of the instructions in the microprocessor falls back a bit.

The DMA Controller obtains the access for the system buses by repeatedly issuing the requests using the Bus Request (BR) and Bus Grant (BG) signals until the entire data block has been transferred.

Though the information bytes are not transferred as fast as in the Burst mode, the only advantage of the cycle-steal mode is that the CPU does not remain idle for long durations of time, as in the burst DMA mode. This method is mainly used in controllers which are used in monitoring data in real-time.

Transparent or Hidden DMA transfer

  • The Hidden DMA Transfer method is considered the slowest among all the other DMA transfers.
  • Here, the microprocessor executes some of its states during which it floats the data bus and the address bus.
  • In these states, the microprocessor gets isolated from the main system bus.
  • In this isolation, the DMA controller transfers the information byte between the external peripherals and the memory. This, thus, becomes transparent to the microprocessor.
  • The instruction execution speed of the microprocessor does not get reduced. However, this DMA mode requires extra logic to sense the states in which the processor is floating the buses.
  • This mode is favored at the time when we do not want the CPU to stop executing its main program, as the data transfer is performed only when the CPU does not need the system bus.
  • Nevertheless, the hardware needed to check such states can be pretty complex and a little too expensive as well.

Serial Data Transfer Techniques

Under the serial data transfer mode, a single bit of information/data is transmitted on a single line at a time. But how would the 8085 accomplish this?

An 8-bit parallel word is first converted into a stream of 8 serial bits, with the help of a parallel – to – serial converter. In the same way, during the serial reception of information bits, the microprocessor receives a stream of separate 8 bits, one by one, which are later converted to an 8-bit parallel word with the help of a serial – to – parallel converter.

Serial data communication can be categorized on the basis of how data transmission occurs. These are:

  • Simplex: In simplex communication, the hardware is set such that the data exchange takes place in only one direction. Example: Computer to Printer communication.
  • Half Duplex: The half-duplex communication allows the data exchange in both directions, but not at the same time. Example: Walkie talkie.
  • Full Duplex:  It permits the information transfer in both directions at the same time. Example: Telephone lines.

The information in serial communication can be transmitted in two ways. They are:

  • Synchronous Serial Data Transfer
  • Asynchronous Serial Data Transfer

Let us study each of these transfer schemes in detail.

Asynchronous Serial Data Transfer

The Asynchronous formats are more character-oriented. Here, the bits/character/data word are sent together at a constant rate, but the characters can arrive at any rate i.e., asynchronously, provided that these do not overlap. If no characters are being transmitted over the line, the line stays HIGH at Logic 1 called MARK. Logic 0 is called SPACE.

At the transmitter end

  • When a character (data bits) is to be sent, it is indicated by a start bit, which is always a logic 0 signal (coming down from a logic 1).
  • This signal then synchronizes the transmitter and the receiver.
  • Following this bit, the information bits are sent one bit at a time, with the Least Significant Bit sent first (D0-D7).
  • The size of the character (number of bits) can vary and depends on the system requirement.
  • Once all information is sent, a parity bit might be sent at the end.
  • After that, the stop bit(s) is sent, which is a high signal.
  • This stop bit indicates the end of transmission of the information bits.
  • The start and stop bit carry no information but are just indications for the commencement and end of data exchange.
  • The combination of the start bit, the character bits, and stop bits is known as a frame.
  • This mode is used in the low-speed transmission of information, where speed might be less than 20kbps.

At the receiver end

  • The output of the transmitter is the input to the receiver.
  • The receiver is always on the lookout for the high signal transitioning into a low signal.
  • Once it detects a high signal that transitions into a low, it considers the low bit to be the start bit and only then starts accepting data.
  • Once all the data is transferred, the receiver waits for the stop bit to restart looking for the next start bit.

Synchronous Serial Data Transfer

  • In the asynchronous data transmission method, the start and stop bits included in every frame are the wasted overhead bytes, which reduces the overall character rate.
  • We can avoid using the start and stop bits for every frame of data by synchronizing the transmitter and the receiver instead. Once synchronized, any size of data can be transferred serially.
  • This synchronization can be done by placing synchronous bits in the place of the start and stop bits.
  • Such a protocol is known as synchronous serial communication.
  • These synchronous bits are transferred by the transmitter. And at the receiver end, the receiver waits to detect these two or three sync bits.
  • Once detected, the transmitter and receiver are said to be in sync and data transmission begins.
  • Characters are received at a constant rate here, and the data transfer takes place in blocks.
  • Synchronous serial data transfer is ideal for high-speed transmission of information.
  • If no data bits exist, the transmitter still keeps transmitting the sync bits to keep the synchronization intact.

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