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8051 Memory Organization – ROM and RAM Structure

As we saw in our post on the difference between microprocessors and microcontrollers, a microprocessor is an IC which only has a CPU inside it. It does not have RAM, ROM, or any other peripherals on the chip. A user/ system designer has to externally install these peripherals to make the system functional.

In contrast, a microcontroller is a device that consists of a fixed RAM, ROM, and other peripherals like timers, interrupts, ports embedded on a single chip. Since the applications are specific, it requires a small amount of on-chip RAM and ROM, which in turn reduces the cost, size and removes overhead in terms of having to interface everything before having a workable computing device.

In this post, we will learn about the internal RAM and ROM of the 8051. We will also discuss the addition of external memory. However, the actual interfacing part is covered in a separate post here.

Let’s take a look at a flowchart depicting the general classification of memory in an embedded system.


Memory classification in a Microcontroller

ROM: Read-only memory (ROM) is a type of storage that permanently stores data on electronic devices. It contains the code or program that is needed to start a PC; it performs major input/output tasks and holds programs or software instructions.

RAM: Random Access Memory is the main memory in a computer, and it is much faster to read from and write to than other kinds of storage, such as a hard disk drive (HDD), solid-state drive (SSD) or optical drive.

Importance of memory in 8051 Microcontroller

The basic difference between a microprocessor and a microcontroller is the on-chip memory. A microcontroller consists of an on-chip RAM (Data Memory) and ROM (Program Memory). The Program Memory is used for permanent saving of the code or program that is to be executed in the PC (Program Counter), whereas the Data Memory is used to temporarily store intermediate results and variables. For a CPU to process the information, it should be stored in either RAM or ROM; these are referred to as primary memory.

Block diagrams of 8051 Microcontroller Memory

 Figure address MOV, MOVC, and MOVX instructions   

Program memory organization in 8051

The Program Memory or ROM is a type of non-volatile memory used in microcontrollers where the code or the program to be executed is stored using the program counter (PC), like tables or initialization program. Intel 8051 has an internal/ built-in ROM of 4KB and can be extended up to 64KB by using an external program memory. The program memory allocation can be done in two ways depending on the status of the EA(bar) pin (External Access Pin), which is an active low pin (i.e., activates when low-signal is provided).

Modern variants of the 8051 uC or chips that are built using the 8051 core have more on-chip memory than the original MCS-51.

External Program Memory

  1. Internal Program Memory (4KB) i.e. from 0000H to 0FFFH + External Program Memory (60KB) i.e. from 1000H to FFFFH. This mode is selected by making EA(bar) = 1. (Refer to fig.1)
  2. Total External Program Memory (64KB) i.e., over the entire range of 0000H to FFFFH. This mode is selected by making EA(bar) = 0. (Refer to fig.2)

Note: The external storage is addressed and accessed via I/O ports P0 and P2. In 8051, the PSEN(bar) = 1 (is active) when reading a byte from external program memory (ROM). The command used to access external ROM is,

MOVC A, @A+DPTR

Interfacing external program memory (1)

Interfacing external program memory (2)

Data memory organization in 8051

The Data Memory or RAM is a volatile memory since cutting off power to the IC will result in loss of information or data. RAM is used for temporarily storing the data and the auxiliary results generated during the runtime. Older version of 8051 used to consist built-in 256 bytes of RAM now, and it consists of an additional 128 bytes, which are accessed by indirect addressing.

Layout of the RAM in 8051

The data memory in 8051 is divided into three parts:

  1. Lower 128 bytes (00H – 7FH), which are addressed b either Direct or Indirect addressing. Further, the Lower 128 bytes are divided into three parts,
    1. Register Banks (Bank 0,1,2,3) from 00H to 1FH – 32 bytes
    2. Bit Addressable Area from 20H to 2FH – 16 bytes
    3. General Purpose Register (Scratch Pad Area) from 30H to 7FH – 80 bytes
  2. Upper 128 bytes (80H – 0FFH) for the Special Function Register (SFRs) which includes I/O ports (P0, P1, P2, P3), Accumulator (A), Timers(THx, TLx, TMOD, TCON, PCON), Interrupts(IE, IP), Serial Communication controls(SBUF, SCON), Program Status Word (PSW). These are addressed using Direct addressing.
  3. 128 bytes of Additional Memory

Register Banks

You know registers as something that is used to store information temporarily. But dividing into register banks is an interesting concept that helps utilize memory effectively. It allows you to address an entire range of memory using just the register’s name.

The 8051 has four Register Banks with each bank having 8 “R” registers, which are used in many of its instructions. These R registers are numbered from 0 through 7 (R0, R1, R2, R3, R4, R5, R6, and R7). These registers are generally used to assist in manipulating values and moving data from one memory location to another. For example, to add three numbers say, 0AH, 0BH, 0CH, we would execute the following instruction:

;By default bank 0 is selected.          
MOV R0, #0CH ;Make R0 = 0CH 
MOV R1, #0BH ;Make R1 = 0BH
MOV A, #0AH ;Make A = 0A
ADD A, R1 ;add A to R1 and save result in A, A = 0AH + OBH = 15H
ADD A, R0 ;add A to R0 and save result in A, A = 16H + 0CH = 21H

Figure depicting the classification of register banks

These banks are accessed one at a time by bit addressing of D3 and D4 bits of PSW (Program Status Word) SFR by changing the values of RS0 and RS1 by SETB, and CLR commands. For example, “SETB PSW.3” will set PSW.3 = 1, and Bank 1 register is selected. By default, Bank 0 is selected.

RS1 (PSW.4) RS2 (PSW.3) Bank Selected Memory Location
0 0 Bank 0 00 – 07
0 1 Bank 1 08 – 0F
1 0 Bank 2 10 – 17
1 1 Bank 3 18 – 1F

Bit addressable memory area

16 bytes of RAM is allotted as a bit addressable memory. It consists of 16 x 8 = 128 bits. These 128 bits can be individually bit-addressed, starting from 00H to 7FH or can be byte-addressable for 20H to 2FH.

A quick analogy to comprehend this would be the one we used in our 8085 course. Consider a housing society with 16 lanes named 20H, 21H, 22H, … , 29H, 2AH, 2BH, … , 2EH, 2FH, with each row consisting of 8 houses, and each house has its particular address in the range of 00H TO 7FH, i.e., 128 houses. Now, these houses can be addressed individually one at a time, or the whole lane can be addressed at a time.

These bits can be modified by using SETB and CLR commands. The PSW SFR has an F0 flag, which is a user set flag, this flag can be copied to bit addressable memory for monitoring its status. You can check out a list of all the bitwise instructions in 8051 over here.

Bit addressing is very useful when we want to monitor the status of a particular pin of any port (say, P1.1) i.e., if we want to turn ON/OFF an LED connected to a particular pin we don’t need to write the contents to the whole port,  instead, we can address the particular pin to which the LED is connected and save memory.

Let’s take some examples to understand bit addressing, refer to the below figure for better clarity.

CLR 0FH ; D7 bit of RAM location 21H = 0
SETB 42H ; D2 bit of RAM location 28H = 1
CLR 67H ; D7 bit of RAM location 67H = 0
SETB 28H ; D0 bit of RAM location 25H = 1

RAM Structure 128+128 bytes

General-purpose area/Scratchpad area

The rest of the RAM from 30H to 7FH, these 32 bytes can be addressed directly or indirectly using direct or indirect addressing modes, respectively. Therefore it’s also called Scratch Pad Memory. You may read or write a full byte (8-bit) data at these locations.

Examples of Direct Addressing:

MOV A, 4 ;reads the contents of address 04H to accumulator and is the same as
MOV A, R4 ;which means to copy R4 into A.

Examples of Indirect Addressing:

MOV A, #55H ;load A with 55H
MOV R0, #40H ;load the pointer R0, R0 = 40H
MOV @R0, A; copy A into the location of RAM pointed by R0

Stack pointer

In 8051 internal RAM can be used as Stack. The stack is an area of the internal RAM that is assigned to temporarily hold all the parameters of the variables, i.e., its value and location/ address.

The stack is also responsible for reminding the order in which a function is called so that it can be returned correctly. We will learn more about the practical application of a stack when we study interrupts in 8051.

The register used to access this stack is called the stack pointer. The address of the stack is contained in the stack pointer register, which itself is present at the location 80H. It is accessed by basic MOV commands, and data is written into or extracted from the stack with the help of PUSH and POP commands.

MOV SP, #07H ;By default SP is initialized to 07 to avoid mix-up with the registers.
PUSH acc ;The stack pointer incremented by 1 first and then the content of the
         ;accumulator is stored in that stack location which is stored in SP.
POP acc ;The data is retrieved from the location of SP into the
        ;accumulator and then SP Is decremented by 1.

External data memory

External data memory is read or write memory. Since external data memory is indirectly accessed through a data pointer register, DPTR (which must be loaded with an address), it is a slower process compared to accessing the internal data memory.

Note that the additional 128 bytes of memory is interfaced with RAM by the use of RD read signal, RD(bar) = 1 (is active) when reading bytes from the external data memory (RAM). The command used to access data from external RAM is,

MOVX A, @DPTR

We hope that this article was able to shed some light on the internal memory organization of the 8051. Remember that we can expand the total memory addressable by the 8051 by interfacing it with external memory chips. We’ll see how to do that further along in this 8051 course.

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