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Working of MOS transistors – Ideal IV characteristics of a MOSFET

The MOSFET is the most commonly used compact transistor in digital and analog electronics. It has revolutionized electronics in the information age. In this article, we will see the basic principle of the working of MOSFETs and also look at a basic derivation for the IV characteristics of the NMOS transistor.

The flow of current is established in a MOSFET device due to the formation of an inverted charge layer. This inversion of charge is controlled by the controlling terminal called the “Gate terminal.” Thus, this controlling action of the current between two terminals called the “Drain,” and the “Source” by a third “Gate” terminal is what gives us the transistor action. We will see each concept in detail as we move forward.

Structure of MOSFET

3-D structure of an NMOS transisor
3-D structure of an NMOS transistor

There are four types of MOSFETs available, but for this article, we will focus mainly on only one of these four types. MOSFETs can be divided into two categories which are:

  • Enhancement Mode MOSFET:
    For this kind of MOSFET, there is no inversion layer present when we apply zero voltage at the gate terminal. On applying a gate voltage which surpasses a certain threshold voltage, we get an inversion in the bulk, and conduction between source and drain takes place. The structure for an enhancement-mode NMOS transistor (n-channel transistor) is shown in figure 1.
  • Depletion Mode MOSFET:
    For a depletion-mode MOSFET, an inversion channel exists even when we apply zero voltage, as shown in figure 2. This is due to the fact that the threshold voltage of a MOS device with a p-type substrate can be negative, i.e., the electrons are already present when there is zero gate voltage.

For this article, we will only stick to Enhancement-mode MOSFET operations. The p-channel MOSFET structures are very similar. One will just have the source and drain of p-type semiconductors, and the substrate will be made of n-type.

Cross section view of an n-channel Enhancement type MOSFET
Figure 1: Cross-section view of an n-channel Enhancement type MOSFET
Cross section view of an n-channel Depletion Mode MOSFET
Figure 2: Cross-section view of an n-channel Depletion Mode MOSFET

The gate is a metal layer (in present-day CMOS technology, this is generally made up of polysilicon) shown by black color, which is deposited over an insulator. A layer of hatched lines shows the insulator (generally, this insulator is made up of Silicon-di-oxide). Some of the common notations used are V_{T}  for the threshold voltage of the MOS device, t_{ox} for the thickness of the oxide layer, C_{ox} for the capacitance per unit area of the oxide layer.

Difference between PMOS and NMOS

From now, we will be mainly considering an n-channel enhancement type MOSFET by default until mentioned otherwise. But the derivation of I-V characteristics and the concepts regarding transistor action are very analogous for a p-type also. Thus, understanding the n-type MOSFET or NMOS will suffice.

Some differences between the PMOS and the NMOS transistor are shown below. Keeping these differences in mind will help in getting a better understanding of the analogy between NMOS and PMOS transistors.

NMOS Transistor PMOS Transistor
Source and Drain is made up of n-type semiconductor Source and Drain is made up of p-type semiconductor
Substrate/Body is made up of p-type semiconductor Substrate/Body is made up of n-type semiconductor
The majority carriers in the inversion channel are electrons(n-type) The majority carriers in the inversion channel are holes(p-type)
The threshold voltage is a positive quantity The threshold voltage is a negative quantity
Can be switched faster because the mobility of electrons is more than that of holes Switching is slower because of holes being the majority carriers

Biasing scheme for NMOS transistor

In this section, we will see a common biasing scheme for the NMOS. The biasing diagrams are shown in figure 3 and figure 4.

We’ll discuss “Body Effect” in the next article on non-ideal IV characteristics due to second-order effects.

For this simple biasing scheme, we have connected the Body terminal with the ground terminal. As shown in the diagrams, the source terminal is connected to the ground. We have connected a voltage source of V_{GS} between the ground and the gate terminal. This will be our controlling voltage. Next, we connect a voltage source between the source and the drain V_{DS}. This source supplies the current when the transistor is on.

 

Biasing of a n-channel Depletion-mode MOSFET (When Gate-to-Source voltage is lower than Threshold voltage)
Figure 3: Biasing of an n-channel Depletion-mode MOSFET (VGS < VT)

 

Biasing of a n-channel Depletion-mode MOSFET (When Gate-to-Source voltage is higher than Threshold voltage)
Figure 4: Biasing of an n-channel Depletion-mode MOSFET (VGS > VT)

Intuitive understanding of the IV characteristics

Before moving on to the mathematical derivation of the IV curves, there is some inherent understanding that can be achieved by observing the diagrams.

The threshold voltage V_{T} here is a property of the MOS structure. Intuitively we can understand it as the minimum voltage that is required to be applied at the gate terminal in order to convert the p-type semi-conductor into an n-majority semi-conductor. Details on this can be found in chapters regarding MOS capacitors on any standard texts.

Different cases of biasing voltage

When V_{GS} < V_{T} i.e., the gate voltage is less than a certain threshold, the transistor is said to be in “Cut-Off.” No inversion layer is formed, and thus there will be no conduction resulting in I_{D} = 0 A.

When we have a V_{GS} > V_{T}, then for a positive voltage applied at the drain w.r.t. source, the electrons in the source will be drawn towards the drain. Thus electrons will get into the source and come out of the drain. As per the conventional direction of the current, the current will go into the drain and will come out of the source. For this V_{GS} value, the transistor can either be in “Triode region” or in “Saturation Region” depending upon the value of V_{DS}.

The three modes of operation i.e., Cut-off, Triode (also referred to as linear region), and Saturation, will be discussed in detail once we start to derive the ideal IV characteristics properly.

Dependence of  current on the voltages applied

By intuition, we can easily deduce that the current I_{DS} will increase as we increase the V_{GS} value because there will be more negative-charge carrier density in the inversion layer and hence more conductance(low resistance). Also keeping the V_{GS} (> V_{T}) constant and increasing the V_{DS} will also result in the current I_{DS} to increase as there will be more potential difference applied between the source and the drain.

Mathematical derivation of ideal IV characteristics

In this section, we will solve some equations, which are an outcome from MOS capacitor physics and its operation in order to get the ideal IV characteristics of an NMOS device.  The details regarding different modes of operation will also be discussed in this section.

Cut-Off Mode

In this mode of operation, the V_{GS} is less than V_{T}. Hence, there will be no inversion layer formation resulting in almost zero conductance between the drain and the source. Thus, our drain current will anyway be zero. So, in this region of operation I_{DS} = 0 A.

Linear Mode (Triode Mode)

Zoomed-in view of NMOS channel for drain-to-source voltage less than the overdrive voltage
Figure 5: Zoomed-in view of NMOS channel for VDS < VGS – VT

In figure 5, you can see the zoomed-in view of an NMOS transistor’s channel when it is conducting. We will first derive the IV relation for this configuration.
Suppose we take the voltage across the oxide layer at any point “x” distance away from the source terminal to be V_{x}. And the voltage in the channel at a distance of “x” from the source is V(x). After solving for the physics of MOS capacitor, we can conclude that the negative charge carriers that accumulate below the oxide layer is proportional to the value of V_{x} i.e. proportional to [(V_{GS} - V_{T}) - V(x)]. Note that we deduct the threshold voltage from the actual voltage difference; we can think of this as an off-set term. The value V_{GS} - V_{T} is also referred to as overdrive voltage(V_{OV}).

The exact equation for charge per unit length in the inversion layer is given by :

Q(x) = W C_{ox} V_{x} , replacing V_{x} with (V_{GS} - V_{T}) - V(x), we get:

 Q(x) = W C_{ox} \{(V_{GS} - V_{T}) - V(x)\}

Hence, at the source-edge, we have: Q(x) = W C_{ox} (V_{GS} - V_{T}) as V(x) = 0 (the source is grounded). Here Q(X) represents the charge per unit length at steady state along the length “L” of the transistor from the source to the drain as shown in the diagram of figure 5.

We have velocity of electrons in the inversion layer given by:

 v = -\mu_{n} \vec{E};

Here \vec{E} is the electric field in the channel with direction from drain to source. \mu_{n} is the mobility of the electrons.

And we also have: \vec{E} = \frac{dV}{dx}

Current due to the majority charge carriers i.e. electrons in the inversion layer is given by:

current = -I_{D} = v Q(x) .

(Note that the direction of current has already been considered in this equation, I_{D} is taken in the conventinal sense)

Hence, from these equations, we get a differential equation given as:
-I_{D} = {-\mu_{n} \frac{dV}{dx}} \times W C_{ox} [(V_{GS} - V_{T}) - V(x)]  I_{D} = \mu_{n} \frac{dV}{dx} W C_{ox} [(V_{GS} - V_{T}) - V(x)]  I_{D} dx = \mu_{n} W C_{ox} [(V_{GS} - V_{T}) - V(x)] dV(x)

We integrate for both sides of the equation where x goes from 0 to L and V(X) goes from 0(at the source) to V_{DS}(at the drain):

 \int_{0}^{L} I_{D} dx  = \int_{0}^{V_{DS}} \mu_{n} W C_{ox} [(V_{GS} - V_{T}) - V(x)] dV(x)

The current through the inversion channel is constant and hence I_{D} will have no variation w.r.t. x. Thus the above mentioned integrals simplifies into:

 I_{D} L = \mu_{n} W C_{ox} [(V_{GS} - V_{T}) V_{DS} - V^{2}_{DS}/2] Therefore finally we get our drain current as a function of V_{DS} and V_{GS} to be:

I_{D} = \frac{\mu_{n} W C_{ox}}{2 L}[2 (V_{GS} - V_{T}) V_{DS} - V^{2}_{DS}]

Now, suppose we are operating at a point where our V_{DS} is very close to zero, hence we can neglect the square term w.r.t. the linear term in the current equation. This means that approximately we can write:

I_{D} = \frac{\mu_{n} W C_{ox}}{L} [ (V_{GS} - V_{T}) V_{DS}]

Looking at the equation, we can see that if the drain-to-source voltage is much lower than the overdrive voltage, then the current varies linearly with the V_{DS}. Hence, we call this region of operation as “Linear”.

Saturation Mode operation

The current I_{D} varies in a parabolic manner w.r.t. V_{DS}. But as we keep on increasing the drain-to-source voltage V_{DS}, we make the n-type semiconductor at the drain more and more reversed bias w.r.t. the p-type body which is grounded.

Zoomed-in view of NMOS channel for drain-to-source voltage is equal to the overdrive voltage
Figure 6: Zoomed-in view of NMOS channel for VDS = VGS – VT

Thus after a certain point, we will see a phenomenon called “Pinch-Off”. This is shown in figure 6 where the inversion layer thickness goes to zero at the drain terminal edge. This means that the charge in the inversion layer at that point is zero. As we had the charge proportional to  (V_{GS} - V_{T}) - V(x) , we can say that for x = L, V(L) =  V_{DS} , Q(x = L) = 0. This means the point where pinch-off starts is given by:

 V_{DS} = V_{GS} - V_{T} = V_{OV}

After this point, I_{D} is no longer a parabolic curve and the transistor in “Saturation-Mode”.

Zoomed-in view of NMOS channel for drain-to-source voltage is more than the overdrive voltage
Figure 7: Zoomed-in view of NMOS channel for VDS > VGS – VT

Figure 7 shows the inversion layer of a transistor in saturation. We will derive the IV relation for the transistor in saturation by making some small changes in our original differential equation.

In the diagram, the point where the inversion charge becomes zero is given by x = L’. This means that at this point we have : V(x = L’) = V_{GS} - V_{T}. Beyond this point, there is a depletion layer with high electric field. Thus, electrons arriving at the point x = L’ are swept to the drain terminal by the electric field.

Thus, this time we will integrate from x=0 to x=L’ and our V(X) will rum from 0 (at source) to V_{GS} - V_{T}(at the point of pinch-off):

\int_{0}^{L'} I_{D} dx  = \int_{0}^{V_{GS} - V_{T}} \mu_{n} W C_{ox} [(V_{GS} - V_{T}) - V(x)] dV(x)

After solving and simplifying the equation, we get:

I_{D} = \frac{\mu_{n} W C_{ox}}{2 L'} [(V_{GS} - V_{T})^2]

For most of the practical cases, the actual channel length L’ is almost equal to L(original channel length of the MOSFET). The exact effect which changes the drain current due to variation in L’ is called “Channel Length Modulation”. This will be considered in the next article.

Plots showing the IV Characteristics

In this section, we will summarize the final equations we obtained for different regions of operation and see the corresponding ideal IV curves we get for an NMOS transistor.

Drain Current variation with Drain-to-Source Voltage

For the following plots, we have considered that \frac{\mu_{n} W C_{ox}}{L} = 2 mA/V^2 . The threshold voltage for out NMOS is considered to be V_{T} = 0.5 V. The practical values of these parameters are very similar to the ones we have assumed. Nonetheless, we must focus on the type of curves we obtain and not the exact numeric values.

  • In Cut-Off Mode, the drain current I_{D} = 0 A.
  • In Linear Mode, I_{D} = \frac{\mu_{n} W C_{ox}}{2 L}[2 (V_{GS} - V_{T}) V_{DS} - V^{2}_{DS}]
  • In Saturation Mode, I_{D} = \frac{\mu_{n} W C_{ox}}{2 L'} [(V_{GS} - V_{T})^2]
IV characteristics in the linear region
Figure 8: NMOS I-V Characteristic in Triode Region i.e. VDS < VOV
IV characteristics in the linear region
Figure 9: NMOS I-V Characteristic in Triode Region for VDS very close to zero

The plots in figure 8 and figure 9 show the IV characteristics of the NMOS that we have considered in its linear mode of operation. The parabolic nature of the curve can be seen in figure 8. If we zoom-in the same plot near the origin, then we can see that the curves are almost linear which is the reason this region is named “Linear Region”.

Final IV characteristics for a NMOS with threshold voltage of 0.5V
Figure 10: Final IV Characteristics for an NMOS transistor with VT = 0.5 V 

In figure 10, the final IV characteristics of the NMOS is shown for different values of V_{GS}. We can observe that the drain current  I_{D} saturates to a constant value once the drain-to-source voltage V_{DS} goes beyond the overdrive voltage V_{OV}.

Drain Current variation with Gate-to-Source Voltage

Here we also consider a transistor for which \frac{\mu_{n} W C_{ox}}{L} = 2 mA/V^2 but we will see different curves considering different values of threshold voltage V_{T}.  The curves shown in figure 11 and figure 12 are obtained, keeping the transistor in its saturation region. This means that the current has a parabolic relation with the gate-to-source when it exceeds the threshold voltage.

Drain current variation with gate-to-source voltage
Figure 11: Plot of Drain Current (ID) vs. Gate-to-Source Voltage(VGS)
Root of drain current variation with gate-to-source voltage
Figure 12: Plot of Root of Drain Current ID vs. Gate-to-Source Voltage (VGS)

An analogy for Ideal IV characteristics of PMOS transistor

We will not be explicitly deriving the IV characteristics for the PMOS device separately because both the derivation and the final curves obtained are very similar to that of NMOS. A diagram showing the biasing scheme for a PMOS transistor is shown in figure 13.

Cross-section view of PMOS transistor showing the biasing scheme
Figure 13: Cross-section view of PMOS transistor showing the biasing scheme

It is observed from this diagram that the directions of the currents and voltages are inverted. For example, if we want to operate the PMOS in its saturation region, then we will apply a positive V_{SG} and also a V_{SD} which is more than the magnitude of V_{T}. The inversion in the direction of the current is also taken into account as the current is now coming out of the drain terminal. In this case, the conduction will be due to the formation of a hole inversion layer when we apply a voltage less than a threshold value(negative in case of enhancement-mode PMOS) at the gate w.r.t. Source. Thus it is clear that in the NMOS, if every quantity gets inverted by a negative sign, then it’s operation will be the same as that of a PMOS.

Conclusion

To conclude, in this article, we have considered the ideal IV characteristics of a MOSFET. We have seen the basic MOSFET structure, different types of MOSFETs, and some basic differences between them. Then we solved for the current and also plotted the current for different cases. But still, while deriving the current, we have assumed certain ideal scenarios. In the next article, we will see the non-idealities in the MOSFET and how it affects the IV characteristics of the MOSFET.

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