We are now going to write the VHDL code for demultiplexer using the dataflow method. And since the dataflow architecture gives us the functionality to code circuits using their truth table, we’ll do just that. Let’s start off by understanding a demultiplexer’s external ports for the entity-architecture pair that we will define later. Then we will take a look at the truth tables.
Explanation of the VHDL code for demultiplexer using dataflow method. How does the code work?
A demultiplexer is a combinational digital logic circuit that assigns one input to one of several output lines. It selects one of these output lines depending on the value of its select inputs. So a demultiplexer has one input signal, select lines, and multiple output lines.
Just like we used the select statement swhen coding for multiplexers. I will reiterate.
VHDL code for demultiplexer using dataflow (logic equation) method – 1:2 Demux
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity DEMUX_SOURCE is Port ( I,S : in STD_LOGIC; O1, O2 : out STD_LOGIC); end DEMUX_SOURCE; architecture dataflow of DEMUX_SOURCE is begin O1 <= I and (not S); O2 <= I and S; end dataflow;
VHDL code for demultiplexer using dataflow (truth table) method – 1:4 Demux
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity DEMUX_USINGTRUTHTABLE_SOURCE is Port ( I : in STD_LOGIC; S : in STD_LOGIC_VECTOR (1 downto 0); Y : out STD_LOGIC_VECTOR (3 downto 0)); end DEMUX_USINGTRUTHTABLE_SOURCE; architecture dataflow of DEMUX_USINGTRUTHTABLE_SOURCE is begin --- since the output is a combination of character and binary bits, bitwise operation with bit and CHARACTER will take place (&) not logical and with S select Y <= ("000" & I) when "00", ("00" & I & "0") when "01", ("0" & I & "00") when "10", (I & "000") when others; end dataflow;