Nest up in this VHDL course, we are going to write the * VHDL code for demultiplexer* using the dataflow method. And since the dataflow architecture gives us the functionality to code circuits using their truth table, we’ll do just that.

Let’s start by understanding a demultiplexer’s external ports for the entity-architecture pair that we will define later. Then we will take a look at the truth tables.

**Explanation of the VHDL source code for a demux using dataflow method. How does the code work?**

A demultiplexer is a combinational digital logic circuit that assigns one input to one of several output lines. It selects one of these output lines depending on the value of its select inputs. So a demultiplexer has one input signal, select lines, and multiple output lines.

We will proceed just like we did with the select statement in the VHDL coding for multiplexers.

**Logic equation for a 1:2 Demux**

Y0 = I0S’

Y1 = I0S

Here, I0 is the input. S is the select line input. Y0 and Y1 are the outputs. To see how we got this equation, you can check out the working of the 1:2 demux.

**VHDL code for demultiplexer using dataflow (logic equation) method – 1:2 Demux**

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity DEMUX_SOURCE is Port ( I,S : in STD_LOGIC; O1, O2 : out STD_LOGIC); end DEMUX_SOURCE; architecture dataflow of DEMUX_SOURCE is begin O1 <= I and (not S); O2 <= I and S; end dataflow;

**Truth table of 1:4 demux**

I0 | S0 | S1 | Y0 | Y1 | Y2 | Y3 |

I | 0 | 0 | I | 0 | 0 | 0 |

I | 0 | 1 | 0 | I | 0 | 0 |

I | 1 | 0 | 0 | 0 | I | 0 |

I | 1 | 1 | 0 | 0 | 0 | I |

**VHDL code for demultiplexer using dataflow (truth table) method – 1:4 Demux**

Usually, we see the truth table is used to code in the behavioral architecture. However, it is possible to use the truth table of a digital electronic circuit in the dataflow architecture too. This demux code is a perfect example of doing that. We’ll be using the truth table to write the demultiplexer’s VHDL source code.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity DEMUX_USINGTRUTHTABLE_SOURCE is Port ( I : in STD_LOGIC; S : in STD_LOGIC_VECTOR (1 downto 0); Y : out STD_LOGIC_VECTOR (3 downto 0)); end DEMUX_USINGTRUTHTABLE_SOURCE; architecture dataflow of DEMUX_USINGTRUTHTABLE_SOURCE is begin --- since the output is a combination of character and binary bits, bitwise operation with bit and CHARACTER will take place (&) not logical and with S select Y <= ("000" & I) when "00", ("00" & I & "0") when "01", ("0" & I & "00") when "10", (I & "000") when others; end dataflow;

**Testbench waveform for 1:4 Demultiplexer**

Were you able to write the VHDL code for your demux? Let us know what you did differently by commenting below. Also, would you like us to include the VHDL code for a 1:8 demux?