In this post, we will take a look at implementing the VHDL code for comparator using behavioral architecture. First, we will take a look at the logic circuit of the comparator. Then we will understand its behavior using its truth table. And then we will understand the syntax. For the full code, scroll down.
Explanation of the VHDL code for comparator using behavioral method. How does the code work?
A comparator is a combinational logic circuit that compares two inputs and gives an output that indicates the relationship between them. There are three outputs. An output that indicates if number A is greater than number B. An output that indicates if it’s smaller. And finally, an output that indicates if the two numbers are equal. Let’s take a look at its logic circuit for some clarity.
Logic circuit for 1-bit comparator
As we can see, the 1-bit comparator has two inputs and three outputs.
Truth table for 1-bit comparator
Through the medium of writing the VHDL code for this logic circuit, we will understand an application of the case statements. We can use these Case statements because we are using behavioral architecture. Generally, throughout this course on VLSI and VHDL programming, I have mentioned that when dealing with truth tables, it is easier to define the entities as vectors. However, in this particular program, we will define the outputs as scalars. The reason is that either way the total lines of code that we will be writing will remain unchanged. So let’s take a look at the syntax for the entity-architecture pair and the begin statements specific to the behavioral model.
entity COMPARATOR_SOURCE is Port ( A : in STD_LOGIC_VECTOR (1 downto 0); G,L,E : out STD_LOGIC); end COMPARATOR_SOURCE; architecture Behavioral of COMPARATOR_SOURCE is
First off, we will set all the outputs to zero. The case statements’ syntax allows us to assign both, condition as well as the output value to an output port in the same line of code. The condition is preceded by a when statement. And the output is simply assigned using the assignment operator.
begin process (A) begin G <= '0'; L <= '0'; E <= '0'; case A is when (A(0)<=A(1)) => E <= '1'; when "01" => L <= '1'; when others => G <= '1';
VHDL code for comparator using behavioral method
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity COMPARATOR_SOURCE is Port ( A : in STD_LOGIC_VECTOR (1 downto 0); G,L,E : out STD_LOGIC); end COMPARATOR_SOURCE; architecture Behavioral of COMPARATOR_SOURCE is begin process (A) begin G <= '0'; L <= '0'; E <= '0'; case A is when (A(0)<=A(1)) => E <= '1'; when "01" => L <= '1'; when others => G <= '1'; end case; end process; end Behavioral;