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VHDL code for an encoder using behavioral method – full code and explanation

In this post, we will take a look at implementing the VHDL code for an encoder using behavioral method. First, we will take a look at the logic diagram and the truth table of the encoder and then the syntax. For the full code, scroll down.

4:2 encoder using gates 4:2 encoder

Explanation of the VHDL code for an encoder using behavioral method. How does the code work?

Encoding means to code some data. A digital encoder takes some data as input and converts it into code. That’s the principle of it. But how? When you have a 2-bit data, you can write it in four ways. 00, 01, 10, and 11. This means that 2-bit data is capable of storing four different types of data.

In a 4:2 encoder, the circuit takes in 4 bits of data as input. It then codes the data to give an output of two bits. Here, we will be writing the VHDL code for a 4:2 encoder using the behavioral modeling style of architecture.

When we talk about the behavioral model, we don’t really need the circuit or the logic equation. All we need is data about the behavior of the circuit. But what do we mean by behavior really? By behavior, we mean, the response or output of a circuit under the application of a certain set of inputs. Does that create a picture in your mind? If it does, it must look a lot like a truth table. And that’s correct. We need the truth table.

Truth table of a 4:2 encoder

ABCDY0Y1
000100
001001
010010
100011

The approach of using case statements for the behavioral code of the encoder is very similar to how we wrote the VHDL code for the decoder using the behavioral model. The only thing that is probably changing between the two programs is the change in the number of I/O ports.

Let’s start off with what we know to be the most important part of every VHDL code. The entity-architecture pair. The entity will have the port declaration statements of four input ports and two output ports. For the sake of ease, we will define them in STD_LOGIC_VECTOR datatype.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity ENCODER_SOURCE is

    Port ( I : in  STD_LOGIC_VECTOR (3 downto 0);

           Y : out STD_LOGIC_VECTOR (1 downto 0));

end ENCODER_SOURCE;

The behavioral code always has a process statement. The sensitivity list variable here would be the input vector ‘I’. We begin the architecture first, define the process, and then begin the process. This order is imperative.

architecture Behavioral of ENCODER_SOURCE is


begin

process (I)

begin

The case sequential statement that we use in VHDL is not to be confused with the switch-case statements that we are accustomed to in C programming language. The syntax is a bit different here.

case I is

when "0001" => Y <= "00" ;

when "0010" => Y <= "01" ;

when "0100" => Y <= "10" ;

when others => Y <= "11" ;

Towards the end, you need to close the begin statements, as well as the case statement.

end case;

end process;

end Behavioral;

Full VHDL code for an encoder using behavioral method

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity ENCODER_SOURCE is

    Port ( I : in  STD_LOGIC_VECTOR (3 downto 0);

           Y : out STD_LOGIC_VECTOR (1 downto 0));

end ENCODER_SOURCE;


architecture Behavioral of ENCODER_SOURCE is


begin

process (I)

begin


case I is

when "0001" => Y <= "00" ;

when "0010" => Y <= "01" ;

when "0100" => Y <= "10" ;

when others => Y <= "11" ;

end case;

end process;

end Behavioral;

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