Verilog course for Engineers – Verilog coding tutorials

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verilog quiz mcqs and interview questions

Verilog Quiz | MCQs | Interview Questions

March 22, 2020

This Verilog quiz is crafted to test your concepts across a broad range of fundamental Verilog concepts. The questions are accompanied by solutions. Pass this quiz to get access to the Verilog course certification quiz. Please ensure that you are logged in before you attempt this quiz.

sr flip flop verilog

Verilog code for SR flip-flop – All modeling styles

March 26, 2020

In this article, we will learn to Describe the SR-flip flop using the three levels of abstraction – Gate level, dataflow, and behavioral modeling. Generate the RTL schematic for the SR flip flop. Write the testbench. Generate simulated waveforms. What is an SR flip flop? Flip Flops are the basic building blocks of sequential circuits. […]

d flip flop verilog

Verilog code for D flip-flop – All modeling styles

March 22, 2020

This post explains the Verilog description of the D flip-flop using the gate-level, dataflow, and behavioral modeling methods.

Operators in Verilog

March 18, 2020

Any language comes with own set of permissible operations. Here are the ones that you can use in Verilog. This post is a systematic representation of all the operators in Verilog with brief descriptions and easy to understand examples of their applications. The usage of operators is an important fundamental concept to understand.

Dataflow modeling in Verilog

March 14, 2020

Dataflow modeling is the second abstraction level in Verilog HDL. A step above gate-level modeling. This post explains the concept, the syntax, rules and the steps to use dataflow modeling to describe digital circuits. Dataflow modeling is perhaps the easiest way to describe a circuit.

gate level modeling in verilog

Gate level modeling in Verilog

March 1, 2020

Gate-level modeling is the lowest abstraction layer of Verilog. In this modeling style, you’ll get up close and personal with the circuit design and code it in terms of its logic gates. Let’s take a look at the structure and syntax that we’ll use to gate-level code any circuit.

behavioral modeling in verilog hdl

Behavioral Modeling Style in Verilog

Behavioral modeling in Verilog is an important modeling style. In this post, we will take a look at all its rules, tools, and available Verilog syntax and structures.

Verilog Code for AND Gate - All modeling styles

Verilog Code for AND Gate – All modeling styles

January 20, 2020

An in-depth tutorial on encoding an AND gate in Verilog with the testbench code, RTL schematic and waveforms using all possible modeling styles.

Verilog Code for OR Gate - All modeling styles

Verilog Code for OR Gate – All modeling styles

January 26, 2020

An in-depth tutorial on encoding an OR gate in Verilog with the testbench code, RTL schematic and waveforms using all possible modeling styles.

Verilog Code for NAND Gate - All modeling styles

Verilog code for NAND gate – All modeling styles

January 29, 2020

An in-depth tutorial on encoding a NAND gate in Verilog with the testbench code, RTL schematic and waveforms using all possible modeling styles.

Verilog Code for NOR Gate - All modeling styles

Verilog code for NOR gate – All modeling styles

February 2, 2020

An in-depth tutorial on encoding a NOR gate in Verilog with the testbench code, RTL schematic and waveforms using all possible modeling styles.

Verilog Code for EXOR Gate - All modeling styles

Verilog code for EXOR gate – All modeling styles

February 7, 2020

An in-depth tutorial on encoding an EXOR gate in Verilog with the testbench code, RTL schematic, and waveforms using all possible modeling styles.

Verilog code for XNOR gate - All modeling styles

Verilog code for XNOR gate – All modeling styles

March 1, 2020

Next up, let’s design the XNOR logic gate in Verilog using gate-level, dataflow, and behavioral modeling. As is tradition, we will also generate its RTL schematic, write a testbench, and validify our code using the simulation waves.

Verilog Code for NOT Gate - All modeling styles

Verilog Code for NOT gate – All modeling styles

March 2, 2020

Finally, we design the NOT logic gate in Verilog using gate-level, dataflow, and behavioral modeling. This is an important logic gate and by this point into the Verilog course, you might as well as take a swing at this yourself without having to read the post. If you get stuck, you can always take a peek.

Verilog code for Full Adder using Behavioral Modeling

Verilog code for Full Adder using Behavioral Modeling

January 15, 2020

A complete line by line explanation, testbench, RTL schematic, TCL output and Verilog code for a full-adder using the behavioral modeling style of Verilog.

verilog code for half subtractor using dataflow modeling

Verilog Code for Half Subtractor using Dataflow Modeling

January 14, 2020

A complete line by line explanation and the testbench and Verilog code for a half-subtractor using the dataflow modeling style of Verilog.

Verilog Code for Full Subtractor using Dataflow Modeling

Verilog Code for Full Subtractor using Dataflow Modeling

January 15, 2020

A complete line by line explanation, testbench, RTL schematic and Verilog code for a full-subtractor using the dataflow modeling style of Verilog.

Verilog Code for Half and Full Subtractor using Structural Modeling

Verilog Code for Half and Full Subtractor using Structural Modeling

January 12, 2020

A complete line by line explanation, implementation and testing of the Verilog code for half and full subtractor using structural modeling.

Verilog code for 2x1 Multiplexer (MUX) - All modeling styles

Verilog code for 2:1 Multiplexer (MUX) – All modeling styles

January 20, 2020

A complete explanation of the Verilog code for a 2×1 Multiplexer (MUX) using Gate level, Dataflow, Behavioral, and Structural modeling along with the testbench.

Verilog code for 4x1 Multiplexer (MUX) - All modeling styles

Verilog code for 4:1 Multiplexer (MUX) – All modeling styles

January 26, 2020

A complete explanation of the Verilog code for a 4×1 Multiplexer (MUX) using Gate level, Dataflow, Behavioral, and Structural modeling along with the testbench.

Verilog code for 8x1 Multiplexer (MUX) - All modeling styles

Verilog code for 8:1 Multiplexer (MUX) – All modeling styles

February 2, 2020

A complete explanation of the Verilog code for a 8×1 Multiplexer (MUX) using Gate level, Dataflow, Behavioral, and Structural modeling along with the testbench.

Verilog Code for Demultiplexer Using Behavioral Modeling

Verilog Code for Demultiplexer Using Behavioral Modeling

January 12, 2020

A complete line by line explanation, implementation and the Verilog code for demultiplexer using behavioral architecture and different statements like case and assignment.

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