Verilog course for Engineers – Verilog coding tutorials

verilog course
Content
Details
Updates

Verilog Code for EXOR Gate - All modeling styles

Verilog code for EXOR gate – All modeling styles

February 7, 2020

An in-depth tutorial on encoding an EXOR gate in Verilog with the testbench code, RTL schematic, and waveforms using all possible modeling styles.

Verilog Code for NOR Gate - All modeling styles

Verilog code for NOR gate – All modeling styles

February 2, 2020

An in-depth tutorial on encoding a NOR gate in Verilog with the testbench code, RTL schematic and waveforms using all possible modeling styles.

Verilog code for 8x1 Multiplexer (MUX) - All modeling styles

Verilog code for 8:1 Multiplexer (MUX) – All modeling styles

A complete explanation of the Verilog code for a 8×1 Multiplexer (MUX) using Gate level, Dataflow, Behavioral, and Structural modeling along with the testbench.

Verilog Code for NAND Gate - All modeling styles

Verilog code for NAND gate – All modeling styles

January 29, 2020

An in-depth tutorial on encoding a NAND gate in Verilog with the testbench code, RTL schematic and waveforms using all possible modeling styles.

Verilog Code for OR Gate - All modeling styles

Verilog Code for OR Gate – All modeling styles

January 26, 2020

An in-depth tutorial on encoding an OR gate in Verilog with the testbench code, RTL schematic and waveforms using all possible modeling styles.

Verilog code for 4x1 Multiplexer (MUX) - All modeling styles

Verilog code for 4:1 Multiplexer (MUX) – All modeling styles

A complete explanation of the Verilog code for a 4×1 Multiplexer (MUX) using Gate level, Dataflow, Behavioral, and Structural modeling along with the testbench.

Verilog code for 2x1 Multiplexer (MUX) - All modeling styles

Verilog code for 2:1 Multiplexer (MUX) – All modeling styles

January 20, 2020

A complete explanation of the Verilog code for a 2×1 Multiplexer (MUX) using Gate level, Dataflow, Behavioral, and Structural modeling along with the testbench.

Verilog Code for AND Gate - All modeling styles

Verilog Code for AND Gate – All modeling styles

An in-depth tutorial on encoding an AND gate in Verilog with the testbench code, RTL schematic and waveforms using all possible modeling styles.

Verilog code for Full Adder using Behavioral Modeling

Verilog code for Full Adder using Behavioral Modeling

January 15, 2020

A complete line by line explanation, testbench, RTL schematic, TCL output and Verilog code for a full-adder using the behavioral modeling style of Verilog.

Verilog Code for Full Subtractor using Dataflow Modeling

Verilog Code for Full Subtractor using Dataflow Modeling

A complete line by line explanation, testbench, RTL schematic and Verilog code for a full-subtractor using the dataflow modeling style of Verilog.

verilog code for half subtractor using dataflow modeling

Verilog Code for Half Subtractor using Dataflow Modeling

January 14, 2020

A complete line by line explanation and the testbench and Verilog code for a half-subtractor using the dataflow modeling style of Verilog.

Verilog Code for Half and Full Subtractor using Structural Modeling

Verilog Code for Half and Full Subtractor using Structural Modeling

January 12, 2020

A complete line by line explanation, implementation and testing of the Verilog code for half and full subtractor using structural modeling.

Verilog Code for Demultiplexer Using Behavioral Modeling

Verilog Code for Demultiplexer Using Behavioral Modeling

A complete line by line explanation, implementation and the Verilog code for demultiplexer using behavioral architecture and different statements like case and assignment.

Top