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Programmable Logic Devices – A summary of all types of PLDs

  • Programmable Logic Devices (PLDs) are devices that work on a programmable logic – the logic (the way to do something) comes from a program code stored in the device. This program code comprises instructions for the device.
  • This program can be changed, edited or replaced on the requirement.
  • PLDs are made using an integrated circuit with a code given to the system.
  • We write the code for PLDs using a Hardware Programming/Description Language.

types of programmable logic devices

Is programmable logic better than fixed logic?

We know what a programmable logic system is. But what is a fixed logic system?

  • As the name goes, a fixed logic system has circuits whose configurations are preset a.k.a permanent.
  • Their instructions perform only a fixed set of operations repeatedly.
  • Once manufactured and programmed, the logic cannot be changed.
  • This system is a fantastic asset for repeated tasks.
  • But one tiny mistake in the manufacturing process like uploading the wrong code in the device, and the entire system is discarded, and a new design is developed.

That’s quite some risk that companies aren’t willing to take unless necessary. Additionally, fixed logic doesnt allow the users to expand or build on their existing functionalities.

Why not settle for something more flexible, easy to work, and more cost-efficient?

  • Thus, programmable logic comes to the rescue. It is easy-to-program, affordable and equipped with better features.
  • Inexpensive software is used to develop, code and test the required design.
  • This design is then programmed into a device and tested in a live electronic circuit.
  • The corresponding performance then decides if the logic needs to be altered, or if the prototype is fit to be determined as the final design itself.

The fixed logic system thus offers limited usability; a programmable logic seems more feasible and beneficial.

What are the Languages used to write Programmable Logic?

We have a wide array of options to code the programmable logic. Languages like PALASM, CUPL and ABEL are often used for programming the low-complexity devices. Higher-level hardware descriptions languages like Verilog and VHDL are preferred for more complex systems.

PALASM

  • Being an early Hardware Description Language (HDL), PALASM translates Boolean logic functions and state transition tables into a fuse map.
  • PALASM is used in Programmable Array Logic (PAL) devices mostly.

ABEL

  • The Advanced Boolean Expression Language (ABEL) is another programming language used for PLDs.
  • It deals with sequential state machines, truth tables, and concurrent equations.
  • It is also used for test vectors.

CUPL

  • Written in C language, the Compiler for Universal Programmable Logic is one of the old languages used for Programmable Logic Devices.

Verilog

  • Verilog is a commonly used language for digital circuits at the register-transfer level of abstraction.
  • This hardware description language can also be applied for analog and mixed-signal circuits, as well as for the fabrication of integrated circuits.
  • We offer a free Verilog course.

VHDL

  • The acronym, VHDL, can be expanded to VHSIC-HDL.
  • The Very High-Speed Integrated Circuit Hardware Description Language (very-long language name, we know), is a hardware description language used for programming related to analog and mixed-signal systems.
  • It is quite a popularly used language.
  • We offer a free VHDL course.

Factory Programmable Devices

  • Factory Programmable Devices are a type of Programmable Logic Device.
  • When we fabricate a device, we make it according to some specifications.
  • After manufacturing the Factory Programmable devices in the factory, they are tested to verify that they match the parameters as per the datasheet.
  • These devices have a wide frequency range; at high temperatures, they are tested for stability after being programmed.

We shall discuss two types of Factory Programmable Devices:

  1. MROM
  2. MPGA

MROM

  • The Masked ROM is a type of read-only storage whose internal information are programmed by the manufacturer itself.
  • This device contains a software mask which is burned in the chip during the designing stage.
  • These chips are produced by arranging the transistors before the manufacturing process is actually started.
  • In systems requiring long term sustainability, MROMs are used.
  • The ICs are initially ‘masked’ during the designing of the ROM, as per the required design.

MPGA

  • A Mask Programmable Gate Array handles extensive logic circuitry.
  • MPGAs consist of arrays of pre-fabricated transistors which can be later customised to user-defined logic circuits.
  • This customisation is done by connecting the transistors with each other as per our system design.
  • Rows of transistors are interconnected to implement any desired logic circuits.
  • These connections can be either within rows or between the rows.
  • Customisation is carried out during the chip fabrication by providing the metal interconnections.
  • As different interconnections are needed for different requirements, a significant investment is required, and it takes much time for manufacturing.
Masked Programmable Gate Array Architecture
Masked Programmable Gate Array Architecture

Field-Programmable Devices

  • Unlike Factory Programmable Devices, Field Programmable Devices cannot be tested after programming.
  • The frequency range is thus limited.
  • Programming can be done using qualified programmers such as BP Micro, or DataIO.
  • All Programmable Logic Devices are generally referred to as Field Programmable Devices.
  • Field programmable devices as a whole became practically feasible after the invention of electronic erasing.
  • Hence, CPLDs are based on EEPROM technology.

SPLD

  • A Simple Programmable Logic Device is used in applications where only a small number of I/Os are required.
  • They consist of only a dozen or so macrocells.
  • SPLDs are the most straightforward, cheapest, smallest and least-power consuming type of Field Programmable Devices.
  • PLDs such as PALs and PLAs are simple PLDs.
Simple Programmable Logic Devices Archutecture
Simple Programmable Logic Devices Architecture

PROM

  • A programmable ROM is a memory device which permanently stores binary information.
  • It differs from a normal ROM because it can be programmed electrically once using a PROM programmer.
  • This programmable logic device has Fixed AND arrays and Programmable OR arrays.
Block Diagram of PROM
Block Diagram of PROM
  • The inputs of the AND array are not programmable. Thus, we generate 2n product terms using 2n AND gates having n inputs each, using n x 2n decoder.
  • This decoder generates ‘n’ minterms.
  • Unlike the AND array, the OR gates inputs are programmable.
  • The output of the AND array are the inputs to this OR array system.
  • Thus, the output of PROM will be as a sum of minterms.

PLA

  • The Programmable Logic Array is a PLD that has both sections of the AND and OR Arrays as programmable, i.e. there is a Programmable AND Array and Programmable OR Array as well.
  • We call these sections as the AND-plane and the OR-plane.
Block Diagram of PLA
Block Diagram of PLA
  • The inputs of the AND gates are programmable.
  • Thus, we can generate the required product terms using the AND Array.
  • The inputs of the OR gates are also programmable.
  • Thus, the output of PAL will be as a sum of product terms.
  • The PLAs can be used in implementing combinational & sequential logic circuits.

PAL

  • The Programmable Array Logic consists of a Programmable AND array followed by a fixed OR array.
Block Diagram of PAL
Block Diagram of PAL
  • The inputs of AND gates are programmable here.
  • Here, we can generate only the required product terms instead of generating all the possible minterms (by using programmable AND gates).
  • But, the inputs of the OR gates are not of programmable type.
  • The number of inputs to each of the OR gates is of fixed type.
  • The output of PAL will be in the form of the sum of products.
  • Manufacturing of PALs is easier when compared to PLAs and are also considerably less expensive.

GAL

  • It is an advanced development of the PAL.
  • A Generic Array Logic has the exact same architecture as a PAL.
  • The only difference that arises is that the programmable AND array of the GAL can be erased and programmed again.
  • The output logic of the GAL device is also reprogrammable.
  • The erasing and reprogramming can be done with a PAL programmer itself.
  • It consists of the programmable logic and the Output Logic Macro Cells (OLMC) that excludes OR gates and flip-flops.
GAL Architecture
GAL Architecture

Electrically erasable PLDs have replaced PALs and PLAs in the practical world. When multiple PLDs are put together to achieve a high density of gates, we get CPLDs.

CPLD

  • If you require a larger number of macrocells for a given application, ranging anywhere between 32 to 1000 macrocells, then a Complex Programmable Logic Device is the solution.
  • They have a higher input to logic gate ratio.
  • Thus we use CPLD in applications involving larger I/Os, but data processing is relatively low.
  • These devices are denser than SPLDs but have better functional abilities.
  • CPLDs are based on EPROM or EEPROM technology.
  • A CPLD is an arrangement of many SPLD-like blocks on a single chip.
  • These circuit blocks might be either PAL-like or PLA-like blocks.
CPLD Architecture Sample
CPLD Architecture Sample

FPGA

  • A Field Programmable Gate Array has an entire logic system integrated on a single chip.
  • It offers excellent flexibility for reprogramming to the system designers.
  • Logic circuitry involving more than a thousand gates use FPGAs.
  • Compared to a normal custom system chip, the FPGA has ten times better integration density.
  • The architecture of an FPGA system consists of many logic blocks, interconnections between them, and Input-output blocks (IOBs).
  • These logic blocks have a lookup table in which the sequential circuitry is implemented.
  • The IOBs provide a simple interface between the internal user logic and the package pins.
  • FPGAs are used in fast counters, designs involving fast pipelines, designs involving lots of registers, etc.

There are three main types of programming for the FPGA :

    1. SRAM Programming
    2. Anti-fuse Programming
    3. EPROM/EEPROM Programming (or Flash Programming)

SRAM Programmed FPGA

  • SRAM programmed FPGA stores the logic cells data configuration in static memory.
  • Here, the interconnected routes are formed using pass transistors, transmission gates & multiplexers.
  • SRAM Programming uses one or two-way switches and mux to define paths.
  • One-way switches are made using a single NMOS transistor, whereas, in two-way switches, the NMOS are placed parallel to the PMOS to form a transmission gate.
  • Between every two logic blocks, three connections are made.
  • One advantage of this system is that you need not take the FPGA out of the circuit for reprogramming.
  • This programming is efficient only until there is power into the system; once the system loses power, the memory is lost.
  • Thus, we need some type of non-volatile memory to store the program. The system also requires an extra program loader.
Architecture of SRAM based FPGA
The architecture of SRAM based FPGA
  • Programming is carried out in two modes – Master mode and Slave Mode
    • Master Mode
      Here, the FPGA reads configuration information from an external source, usually an external Flash memory chip.
    • Slave Mode
      The FGPA is configured by another external master device. This can be either done via a dedicated configuration interface or with a boundary-scan interface.

ANTIFUSE PROGRAMMING

  • Antifuse programmed FPGAs can be programmed only once.
  • An antifuse does not conduct current initially but is ‘burned’ to conduct electricity.
  • This behavior is opposite to that of a fuse, and thus called and antifuse.
  • Since a burned antifuse cannot be undone, this programming cannot be done again.

FLASH

  • The SRAM-programmed FPGAs with internal flash uses the flash memory only on startup for loading the data in the SRAM cells.
  • But Flash programmed FPGAs use the flash as a primary configuration storage resource.
  • This method consumes lesser power, making it a better choice than the SRAM FPGAs.
  • They are also tolerant of radiation effects.
  • These also prevent any unauthorized bitstream copying.

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