Pipeline system in CPUs and Computers to speed up processing

When we were discussing the difference between RISC and CISC architectures in the previous post, we came across a term called ‘pipeline’. A pipeline is a series of units connected in a way that allows the processor to process multiple instructions simultaneously. This is done to increase the operating frequency of the processor.

Is there a simple analogy to understand pipelining?

A common analogy used in classes is that of an automobile assembly line. Imagine for a second, if an automobile manufacturing plant, or any manufacturing plant for that matter, took in just one car at a time.

So the steel sheets would come in. The chassis will be prepared and only after the car is completely made will the assembly line begin work on the next car. This seems inefficient. What if we divide the manufacturing of the car into different stages? And then run all stages simultaneously? With each stage placed in a succession of the previous, we will be able to work on more than one car at the same time. If there are three stages, we will have three cars on the assembly line at the same time. If there are five stages, we will have five cars on the assembly line at the same time. Higher the number of stages, higher the efficiency of the manufacturing plant.

How does a pipeline work in a computer architecture or a processor?

The same principle as seen in the above analogy is applied to processors. The execution of an instruction is divided into stages based on the processor architecture. For example, ARM 7 offers a three-stage pipeline. ARM 9 has a five-stage pipeline and so on.

Let us take the case of an ARM 7 processor. The three stages are Fetch, Decode, and Execute. Use the diagram below to understand the concept better.

This is how six instructions will execute in a three-stage pipeline. Each column is one cycle.

In the first cycle, the processor fetches the instruction from the memory. As you can see, every sPipeline in ARM 7 - 3 stagetage takes one cycle to complete. A feature possessed by RISC processors. Hence, pipelining is possible with RISC architecture. Moving on, in the second cycle, the first instruction moves along the pipeline and reaches stage 2, i.e. Decode. In this cycle, the processor also fetches the second instruction from the memory. So now we have two stages executing simultaneously. The decoding of the first instruction and the fetching of the second. In the third stage, both the instructions move along the pipeline and a third instruction is fetched by the processor.

stages in a pipeline
Work done in each stage of a 3-stage pipeline and a 5-stage pipeline

This whole process is known as the filling the pipeline. As the number of pipeline stages offered by a processor increase, the amount of work done in each stage decreases. Consequently, the processing frequency of the processor increases.

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