Difference between RISC and CISC – Reduced & Complex Instruction Set Computing

The architecture of a processor helps to get the desired output for a specific input. Meaning, for each instruction in an instruction set, the insides of the processor have a specific method of operation. The architecture is essentially the way the hardware of a processor is configured, placed and positioned on a transistor level. Think of it as the internal circuitry of the processor. There are many types of processor architectures. We will be looking at two of them and identifying the difference between RISC and CISC architectures.

Complex Instruction Set Computing (CISC) architecture and Reduced Instruction Set Architecture (RISC) architecture are two categories of architecture. In the early days, CISC was the only architecture. The development of CISC processors came by increasing the focus on hardware so as to increase processing power and backward compatibility. This meant more complex logic circuits, more transistors, and thus more costs. This also added more capabilities to the instruction set of the processor.

When the direction of development began to seek simpler instructions, the focus was shifted from the hardware to the compiler. The idea was to make instructions as simple as possible. And hence the new type of architecture got the name of a Reduced Instruction Set Architecture. By making the instructions simple, the hardware became smaller and faster. The power consumption also came down.

However, this does not mean that RISC is better than CISC. Sure, it may appear so since it is faster. But CISC offers a lot of control to developers, has shorter programs and offers better upward compatibility. Hence modern processors use a combination of RISC and CISC. Modern CISC instruction sets like x86 translate their instructions into RISC instructions on the fly so that they can achieve the same benefits. x86 is fairly CISC. MIPS is very RISC. ARM is in the middle.

Summary of the differences between RISC and CISC

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RISC CISC
Stands for “Reduced Instruction Set Computing”. Stands for “Complex Instruction Set Computing”.
It has fewer instructions and a comparatively smaller instruction set. It has more instructions and a more complex instruction set.
Less addressing modes. More addressing modes.
Fixed instruction size (32 bits) and hence each instruction takes one machine cycle to execute. Each instruction can take 2-10 machine cycles.
Performance is optimized with more focus on software. Performance is optimized with more focus on hardware.
Simple hardware, fewer transistors, and lower manufacturing costs. Complex hardware, more transistors, and higher costs.
Low power consumption. High power consumption.
Pipelining, executing multiple instructions simultaneously is possible. Pipelining is not possible.
Since RISC architecture allows for simpler hardware, more elements can be packed on the chip and this increases speed. Number of external components is higher, this affects speed.
PIC, ARM. x86, 8051.
Applications: Smartphones, PDAs. Applications: Security systems, Home automation.

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