**What are **counters**?**

Counters are sequential logic circuits that, in digital systems, are used to count the number of times an event or instance takes place.

A counter is made by cascading a series of flip-flops. As we know, flip-flops have a clock input. Depending on the type of clock input, counters are of two types

- Asynchronous or ripple counters
- Synchronous counters

Since counters kind of depend on clocks like all sequential circuits, to understand their working, we will consider every clock cycle. Meaning, there will be changes in the states of some flip flops at every clock interval. We will try to understand the working in each clock cycle.

On the basis of the way the counters are used, they are divided into

- Up counters
- Down counters
- Up-down counters
- Decade counter
- Ring counter
- Johnson counter

There are many more types of counters available in digital electronics. But, for now, we will take a look at the above types.

**What is a Mod n counter?**

Mod n or Modulus of n, is a way of referring to the maximum count of a counter. Every counter has a limit with regards to the number they can count up or down to. Mod n expresses that limit. It is an important label for a counter because it gives us the maximum count of the counter, as well as the number of flip-flops present in the counter.

A mod n counter can count up to n events. We can mathematically represent a mod n counter as

n =

n = modulus/maximum event count of the counter. This is the number of states that the counter has.

N = Number of flip-flops connected in cascade

– 1 = Maximum decimal count it can reach. Because binary numbers start counting from 0, so for a counter that can count up to 4 events, its decimal equivalent will be 3 only (0,1,2,3).Example: Mod 8 counter

Mod 8 means n = 8. From the equation above

8 =

Thus, N = 3.

Which means that this is a counter with three flip-flops, which means three bits, having eight stable states (000 to 111) and capable of counting 8 events or up to the decimal number – 1 = 7.

## What is a synchronous counter?

In a synchronous counter, all the flip-flops are synchronized to the same clock input. This means that for every clock pulse, all the flip-flops will generate an output. Since the clocking is done in a parallel manner, synchronous counters are also known as parallel counters/simultaneous counters. We can use JK flip-flop, D flip-flop or T flip-flops to make synchronous counters. In this post, we will be using the D flip-flop to design our counters. The methodology for designing the counters with other flip-flops vary with the type of flip-flops.

**What are up counters, down counters and up-down counters?**

Well as their names imply, up counters count upwards or in an incremental manner. Down counters count downwards or in a decremental manner. Up-down counters have the ability to count both upwards as well as downwards.

**How to design a 2-bit synchronous up counter?**

Step 1: Find the number of flip-flops and choose the type of flip-flop.

Since this is a 2-bit synchronous counter, we can deduce the following. There will be two flip-flops. These flip-flops will have the same RST signal and the same CLK signal. We will be using the D flip-flop to design this counter.

Step 2: Proceed according to the flip-flop chosen.

Since we are using the D flip-flop, the next step is to draw the truth table for the counter.

The counting should start from 1 and reset to 0 in the end. So the display would start with displaying 1, 2, 3 and then 0.

**Truth table for the 2-bit synchronous up counter**

Here’s what the truth table will look like. Q represents previous output and Qn represents the current output.

Q1 |
Q0 |
Qn1 |
Qn0 |

0 | 0 | 0 | 1 |

0 | 1 | 1 | 0 |

1 | 0 | 1 | 1 |

1 | 1 | 0 | 0 |

Another handy tip for designing synchronous counters using D flip-flop is that for the 1st flip-flop, you have to connect the inverted output to the input directly. You don’t have to perform any extra logical operation. So, in this case, we will calculate the equation for only Qn1 to be fed back to Q1. From the truth table, using the shortcut we saw in our post on digital comparators, we get the following.

Qn1 is high when Q1 is low AND Q0 is high, OR Q1 is high AND Q0 is low. This gives us the following equation

Qn1 =

The resulting circuit for the 2-bit synchronous up counter is as shown below.

**How to design a 2-bit synchronous down counter?**

Step 1: Find the number of flip-flops and choose the type of flip-flop.

Since this is a 2-bit synchronous counter, we have two flip-flops. These flip-flops will have the same RST signal and the same CLK signal. We will be using the D flip-flop to design this counter.

Step 2: Proceed according to the flip-flop chosen.

We will now design the truth table for this counter. The counter should follow the sequence 0, 3, 2, 1, 0, 3, 2, 1.

**Truth table for the 2-bit synchronous down counter**

Q1 |
Q0 |
Qn1 |
Qn0 |

0 | 0 | 0 | 0 |

0 | 1 | 1 | 1 |

1 | 0 | 1 | 0 |

1 | 1 | 0 | 1 |

Hence we can see that the equation that we will derive for Qn1 is same as that for the up counter. The only difference in the construction will be that in the down counter, the output will be taken from the inverted outputs of the flip-flop.

**How to design a 3-bit synchronous up counter?**

We will need three flip-flops. These three flip-flops are synchronous to the same clock input. They will have the same reset signal as well. Since we are using the D flip-flop to construct this, we can straightaway design the truth table.

The sequence will be 1, 2, 3, 4, 5, 6, 7, 0.

Q2 |
Q1 |
Q0 |
Qn2 |
Qn1 |
Qn0 |

0 | 0 | 0 | 0 | 0 | 1 |

0 | 0 | 1 | 0 | 1 | 0 |

0 | 1 | 0 | 0 | 1 | 1 |

0 | 1 | 1 | 1 | 0 | 0 |

1 | 0 | 0 | 1 | 0 | 1 |

1 | 0 | 1 | 1 | 1 | 0 |

1 | 1 | 0 | 1 | 1 | 1 |

1 | 1 | 1 | 0 | 0 | 0 |

We have our shortcut of connecting Qn0 to Q0 directly. For the inputs of the remaining two flip-flops, we will solve the truth table using K-maps to derive the equations.

Thus Qn1 =

And Qn2 =

**How to design a 3-bit synchronous down counter?**

The circuit diagram for the 3-bit synchronous down counter is the same as that of the up counter. The only difference is that instead of attaching the non-inverted outputs to the display port, we will attach the inverted outputs.

**How to design a 3-bit synchronous up-down counter?**

An up-down counter is capable of counting in both incremental and decremental fashion. For a 3-bit synchronous up-down counter, we need three flip-flops, with the same clock and reset inputs. The way to achieve the ability to count in both the directions is by combining the designs for the up and the down counters and using a switch to alternate between them. We know that for the up and down counters, the design of the circuit is same. The only difference is that for the up counter the output is taken at the non-inverting output ports of the flip-flops. Whereas, for the down counter the output is taken at the inverting output ports of the flip-flops. So we have a total of 3+3 outputs. When we combine them. Six outputs and we need one switch input.

From our post on multiplexers, we know that we can use three 2:1 multiplexers connected via their select lines. This would give us six inputs, one select line, and three outputs. Perfect, that is exactly what we need. Sure, we can’t expect your mind to jump straightaway to multiplexers. But remember that multiplexers give you an option of choosing between multiple inputs. So it does an excellent job of being a switch in digital electronics.

The resulting circuit diagram of the up-down counter is shown below.

**How to design a 4-bit synchronous up counter?**

Since this is a 4-bit synchronous up counter, we will need four flip-flops. These flip-flops will have the same RST signal and the same CLK signal. We will be using the D flip-flop to design this counter.

We will start right away with the design of the truth table for this counter. The 4-bit synchronous up counter should follow the sequence 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0.

Q3 |
Q2 |
Q1 |
Q0 |
Qn3 |
Qn2 |
Qn1 |
Qn0 |

0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |

0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 |

0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 |

0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 |

0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 |

0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 |

0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 |

0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |

1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |

1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 |

1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 |

1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 |

1 | 1 | 0 | 0 | 1 | 1 | 0 | 1 |

1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 |

1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 |

1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 |

The input to the first flip-flop D0 will come directly from its own inverted output. We will use Kmaps to find the logic equations for the remaining flip-flops.

Hence the input to the fourth flip-flop will have the following logic expression

Therefore from the Kmap, the input equation for the third flip-flop is

And the equation for the for the second flip-flop is

From the above equations, we obtain the logic circuit for the 4-bit synchronous up counter below.

**How to design a 4-bit synchronous down counter and 4-bit synchronous up-down counter?**

For the 4-bit synchronous down counter, just connect the inverted outputs of the flip-flops to the display in the circuit diagram of the up counter shown above. Whereas for the up-down counter, you can use multiplexers as switches as we saw in the design of the 3-bit synchronous up-down counter.

## What is an asynchronous counter?

In an asynchronous counter, all the clock inputs of the flip-flops have a unique input that is not shared with any other flip-flop in the system. In fact, in an asynchronous counter, only the first flip-flop is given a clock (CLK) input. The output of the first flip-flop is then connected to the clock input of the subsequent flip-flop and so on.

Now, think about the output for a second. A flip-flop is activated when it receives a clock pulse. So the second flip-flop and all the subsequent flip-flops in an asynchronous counter get active when their preceding flip-flop gives an output. Thus, the clock passes as a ripple through the cascade of flip-flops. Hence, asynchronous counters are alternatively also known as **ripple counters**.

**What is the difference between a synchronous counter and an asynchronous counter?**

Synchronous Counters |
Asynchronous Counters |

All flip-flops are given the same clock simultaneously | The flip-flops are not given the same clock |

There is no connection between the output of a flip-flop and the clock input of the next flip-flop. | The output of a flip-flop is given as the clock input to the next flip-flop |

The settling time is equal to the time it takes for the last flip-flop to get activated. This is quite less compared to the asynchronous counters. | The settling time or the time taken for all the flip-flops to get activated is equal to the sum of all the times needed to activate the last flip-flop. |

It is known as a parallel counter | It is known as a serial counter |

This design gets more complicated as the number of flip-flops increases | The design of asynchronous counters is easy |

Faster | Slower |

synchronous

No propagation delay

no ripples

**Handy tip for designing asynchronous counters**

When you are designing asynchronous counters using D flip-flops, all the inputs of the flip-flops are connected to their own inverted outputs. The only difference between an up-counter and a down counter stems from the ports that are connected to the display. For up-counters, the non-inverted output, Q, is connected to the display. Whereas for a down counter, the inverted output, nQ, is connected to the display.

**How to design a 4-bit asynchronous up counter?**

This is an easy circuit to design. We know we are going to have four flip-flops. Only the first flip-flop is going to have a clock input. The clock inputs of the remaining flip-flops have the outputs of their preceding flip-flops as inputs. Finally, the non-inverted outputs of the flip-flops will connect to the display in the order of which flip-flop gets the first clock input. So LSB will be the flip-flop that gets the first clock input. And MSB will be the flip-flop which gets the clock input in the end.

**How to design a 4-bit asynchronous down counter?**

We mentioned above that to design a down-counter there is only one change that you need to incorporate. And that change to the up-counter’s circuit is to take the output from the inverted output ports of the flip-flops. And that is true. However, there is one other thing that you can do. Instead of providing the output from the inverted ports, you can stick with the non-inverted ports. Just instead of taking the clock output from Q, take it from nQ. And you will get your down-counter.

**How to design a 4-bit asynchronous up-down counter?**

The design remains the same. Depending on where you take the clock input from, your output ports for the up-counting and down-counting will differ. Either way, each flip-flop will connect to a 2:1 multiplexer. With the inverted and non-inverted outputs being inputs to the multiplexer. The multiplexers are cascaded together by connecting their select inputs together. We only need one select line because there are only two states to choose. Depending on the value of the select pin, the circuit can now act as both, an up-counter and as a down-counter.

**How to design a decade counter?**

A decade counter counts ten events or till the number 10 and then resets to zero. Remember that reset pin we used in all of our counters above. Now it’s going to come in handy. In fact, using the logic we use to design the decade counter, you can design a counter that can count to any desired number that you wish.

A count till 10 won’t be possible in a 3-bit counter. Because has a maximum count of . A 4-bit counter can count up to 15 though. So let’s use that. Also, we know that the binary number 1010 represents 10. The four digits are a dead giveaway that we are going to be using four flip-flops.

The reset pins function is to clear the inputs of all the flip-flops. So we need to find a way for this circuit to count up to 10 and then reset to 10. At the count of 10, flip-flops 1 and 3 will be high. Up to 10, this is the first time that this configuration will occur. But remember that we are counting 0 too, so to count 10 events we need to actually count up to 9 and not 10. At the count of 9,

0 – 0000

1 – 0001

2 – 0010

3 – 0011

4 – 0100

5 – 0101

6 – 0110

7 – 0111

8 – 1000

9 – 1001

10 – 1010

If we take the outputs from the MSB and LSB flip-flops and connect them to an AND gate, we can get a logic 1 at the count of 9. If we connect the output of this AND gate to the reset pin then we can reset the flip-flops at the 10th count. This will give us the decade counter. Here’s what the final logic circuit for the decade counter will look like.

**How to design a ring counter?**

Just as its name suggests, a ring counter has one of its outputs connect back to the input. Thus making a ring. Ring counters are serial shift registers that act as counters. There are two types of ring counters.

- Straight ring counter – The non-inverting output (Q) of the last flip-flop is connected to the first flip-flop.
- Johnson ring counter/Twisted ring counter – The inverting output (nQ) of the last flip-flop is connected to the first flip-flop.

**How is a ring counter constructed?**

A ring counter is essentially a slightly modified parallel in serial out (PISO) shift register that acts as a counter. How? Simple. We just take outputs from each of the flip-flops and attach them to a display. Here is a logic circuit of a 4-bit ring counter. It has four flip-flops and each of them has its own clock input and a reset signal. Okay now here’s a potentially confusing point. We have seen above that a Mod n counter has N flip-flops. Where n= . Just to reiterate, this does not apply here. Mod still has the same meaning, but for ring counters, you cant use the above equation to get the number of flip-flops.

Mod means the number of states. As we will see in the working of the ring counter. It has the same number of states as the number of flip-flops in the system. So for ring counters, a mod 4 ring counter means it has 4 flip-flops and 4 states. States means the number of counts it can have. This will become clearer when we understand the working of this 4-bit ring counter.

**How does a ring counter work?**

Since its a Parallel In Serial Shift counter, we first need to initiate it by giving it an input. Let’s say we give 1000 as the input. When the first clock pulse appears, the data is loaded to the ring counter. At the second clock pulse, the output of the last flip-flop, 0, gets shifted to the first flip-flop. And the high bit of the first flip-flop moves to the second flip-flop. This continues and repeats itself after every FOUR clock cycles. Since it takes the same number of clock cycles as the number of flip-flops in the system, it means that a ring counter has only N states.

And hence, in the case of ring counters, the number of flip-flops is equal to the number of states. Normal binary counters that we saw above had states. For example, a 4-bit synchronous up-counter had 16 states. It could count 16 events or from 0-15 decimals. So we are losing a significant number of counts here. Once a number is input to the ring counter, it circulates the same pattern for every n clock cycles. n is the number of flip-flops connected to it. Hence, it has a frequency of 1/n and is also known as a divide-by-n counter. Check out the pulse diagram and the truth table below to get a clearer picture of the working.

**Timing diagram of a 4-bit ring counter**

**Truth table of a 4-bit ring counter**

QA |
QB |
QC |
QD |

1 | 0 | 0 | 0 |

0 | 1 | 0 | 0 |

0 | 0 | 1 | 0 |

0 | 0 | 0 | 1 |

Note that a ring counter does not count in an ordered sequence. The count here, as we can see from the truth table, is 8, 4, 2,1,8,4,2,1 and so on.

**What are the advantages and disadvantages of a ring counter?**

A small advantage of a ring counter is that it has an automatically decoded output. However, ring counters have a major disadvantage because they need to be initialized. A number needs to be loaded to the ring counter before the start of the counting process. We had not seen this with any other counter yet. Another disadvantage is that only N states are present compared to the states of the binary counters.

**How to design a Johnson ring counter?**

A Johnson ring counter is another type of a ring counter. The difference between this counter and the straight ring counter is that in a Johnson ring counter, the inverted output of the last flip-flop (nQ) is connected to the input of the first flip-flop. The only difference between the straight ring counter and the Johnson counter is that in the Johnson counter the inverted output of the last flip-flop (as opposed to the non-inverted output in the straight ring counter) is connected as the input to the first flip-flop. Here’s the circuit diagram of a 4-bit Johnson counter and its truth table.

Every number that exits the last flip-flop will be inverted and then given as input to the first flip-flop.

**Truth table of a 4-bit ring counter**

Qa |
Qb |
Qc |
Qd |

0 | 0 | 0 | 0 |

1 | 0 | 0 | 0 |

1 | 1 | 0 | 0 |

1 | 1 | 1 | 0 |

1 | 1 | 1 | 1 |

0 | 1 | 1 | 1 |

0 | 0 | 1 | 1 |

0 | 0 | 0 | 1 |

The truth table starts from 0000. This means that it is sel-actuating. The Johnson counter does not need any input. Moreover, a Johnson counter has more states than a straight ring counter. A binary counter has states, a straight ring counter has N states and a Johnson ring counter has 2N states.