More topics in 8085 Microprocessors Course

8085 Microprocessor MCQ | Quiz | Interview Questions

1. A nibble corresponds to

2. The 8085 has five sign flags

3. The Z flag is set when an ALU operation results in a 0 output

4. The temporary register in 8085 is a ____ bit register.

5. Assertion (A): Microprocessor 8085 has an on-chip oscillator with an inbuilt crystal.

Reason (R): For frequency stability crystal oscillator is preferred.

6. If the source and destination addresses are made implicit the length of instruction is reduced.

7. Which of the following has volatile memory?

8. If a microprocessor uses a 5 MHz oscillator. The duration of one T state is

9. When we use RRC instruction once in 8085, the number is

10. What type of instructions can potentially change the sequence of operations in a program?

11. Seven address and data buses are multiplexed in 8085

12. The Sign flag is set when the contents of the accumulator become negative after an ALU operation.

13. To add two 32-bit numbers using an 8085, how many additions would you need to perform?

14. If contents of F register in 8085 are 01010001, it means

15. Consider the following mnemonics

  1. MOV
  2. ADD
  3. LXI
  4. ADI

16. Handshaking programmed data transfer is also known as

17. The addressing mode shown in the given figure is

8085 quiz question

18. Which of the following 8085 instructions affect all flags except the CY flag?

19. The addressing mode depicted in the given figure is

8085 quiz question 2

20. The DW assembler directive in 8085

21. Which of the following is not an assembler directive in 8085?

22. The issue of a timing difference between a fast processor and slow memory is resolved by

23. Select the true statements

24. The integer range per word length in 8085 is

25. What are the values of the control and status signals in an opcode fetch cycle that enable the memory buffer?

Option IO/\bar { M } S1 S0 Control Signal
1 1 1 0 \bar { RD } =0
2 0 1 0 \bar { RD }=0
3 0 0 1 \bar { WR }=0
4 0 1 1 \bar { RD }=0

26. If the instruction CMP B is executed while the contents of the accumulator are less than that of register B, then which flag will be set?

27. In 8085, the RST instruction will cause an interrupt _______.

28. Which of the following are buses present in 8085?

29. On the execution of PUSH/POP instruction, the contents of the SP are incremented/decremented by

30. The values of odd and even parity flags are ___ and ___ respectively

31. This is a type of interrupt where the external interrupting device supplies the address in addition to the interrupt request.

32. Which mode of Data Transfer Schemes (DTS) has the highest efficiency?

33. The content of the HL pair after the execution of the following instructions is ___.

XRA A
MOV L, A
MOV H, L
INX H
DAD H

34. To set a bit you can use ___ logic and to reset it you can use ___ logic.

35. A stack pointer stores the ____.

36. These commands in a program are not translated into machine instructions during assembly process:

37. The register which holds the information about the nature of results of arithmetic and logic operations is called as

38. An 8-bit microprocessor signifies that the processor has an

39. Contents of opcode from memory are loaded into Instruction Register (IR) in this T-state:

40. What is the purpose of the READY signal in 8085

41. For memory mapped I/O, which of the following is true?

42. In I/O mapped I/O, which of the following is true?

43. RST0 - RST7 are the __________ in 8085.

44. An 8-bit microprocessor can have ___ address lines.

45. DMA refers to:

46. The Program Counter (PC) in a microprocessor is used to

47. Upon the execution of the RET instruction:

48. POP B is a

49. Pick the instruction(s) that resets the accumulator

50. The stack is a set of reserved

51. The frequency of the driving network connected between pins 1 and 2 of 8085 microprocessor is

52. If you wish to save the value of the accumulator on the stack, which of the following instruction will you use?

53. S0 and S1 pins are used for

54. A high on RESET OUT indicates

55. EQU memory directive stores ___ bytes in memory

56. Which of the following instructions have 6 T states?

57. All jump/branch instructions in 8085 use ___________ addressing

58. Stack pointer is stored in

59. Stack is stored in

60.

Which of the following is not true during the execution of an interrupt service routine, which does not contain any EI instructions

61.

The first operation performed in INTEL 8085 microprocessor after RESET is

62.

After the execution of CMP A instruction

63.

The 8085 microprocessor enters into bus idle machine cycle whenever

64.

The microprocessor issues ALE during first T-state of

65.

The content of the A15-A8 (higher-order address lines) while executing “IN 8-bit port address” instruction are

66.

The execution of RST n instruction causes the stack pointer to

67. A sequence of two registers that multiplies the content of DE register pair by two and stores the result in HL register pair (in 8085 assembly language) is

68. Select the correct statement(s). In 8085, the data bus and the address bus are multiplexed in order to:

69. Both, the ALU and the control section of 8085 employs which special-purpose storage location?

70. When we use a frequency counter for measuring frequency, two modes of measurement are preferred: Period mode and frequency mode. There is a certain value below which the period mode is preferred over frequency mode. Assuming that the oscillator frequency is 16MHz, what is the crossover frequency?

71. The output data lines of microprocessor and memories are usually tristated because

72. A software breakpoint is a technique utilized during the debugging of the code. In this technique, breakpoints can be set at certain points in the code. When executed, the program stops execution at these breakpoints where the coder can look for register values and such. And then the execution can be carried forward from that particular breakpoint. Which feature of the 8085 allows for this technique?

73. What will be the value in the memory location 7101H after the execution of the following code? The data at memory location 7100 is A7H.

LXI H,7100H
MOV A, M
CMA
INR A
STA 7101H
HLT

 

74. What will be the value in the memory location 7101H after the execution of the following code? The data at memory location 7100 is 35H.

LDA 7100H
ADD A
ADD A
STA 7101H
HLT

75. SUB R and CMP R, both the instructions subtract the value stored in register R with the contents of the Accumulator and achieve the same result.

76. A programmer's model is ____.


 

About The Writer

CLOSE

Leave a Reply

Your email address will not be published. Required fields are marked *