8085 Microprocessor MCQ | Quiz | Interview Questions Published: March 7, 2020 | Umair Hussaini Last modified on March 25, 2020 Loading... 1. A nibble corresponds to 2 bits4 bits8 bits16 bits Loading... 2. The 8085 has five sign flags TrueFalse Loading... 3. The Z flag is set when an ALU operation results in a 0 output TrueFalse Loading... 4. The temporary register in 8085 is a ____ bit register. 181632 Loading... 5. Assertion (A): Microprocessor 8085 has an on-chip oscillator with an inbuilt crystal. Reason (R): For frequency stability crystal oscillator is preferred. Both A and R are correct and R is the correct explanation of ABoth A and R are correct but R is not the correct explanation of AA is correct R is wrongA is wrong R is correct Loading... 6. If the source and destination addresses are made implicit the length of instruction is reduced. TrueFalse Loading... 7. Which of the following has volatile memory? Magnetic TapeRAMHard DiskDiskette Loading... 8. If a microprocessor uses a 5 MHz oscillator. The duration of one T state is 1 μs0.333 μs 0.2 μs 2 μs Loading... 9. When we use RRC instruction once in 8085, the number is Divided by 4Multiplied by 2Divided by 2Multiplied by 4 Loading... 10. What type of instructions can potentially change the sequence of operations in a program? Logical instructionsData transfer instructionsBranch instructionsArithmetic instructions Loading... 11. Seven address and data buses are multiplexed in 8085 TrueFalse Loading... 12. The Sign flag is set when the contents of the accumulator become negative after an ALU operation. TrueFalse Loading... 13. To add two 32-bit numbers using an 8085, how many additions would you need to perform? 2184 Loading... 14. If contents of F register in 8085 are 01010001, it means S = 0, Z = 1, P= 1, AC = 0 and CY = 1.S = 0, Z = 1, AC= 1, P = 0 and CY = 1.S = 0, Z = 1, CY= 1, P = 0 and AC = 1.Z = 0, S = 1, AC= 1, P = 0 and CY = 1. Loading... 15. Consider the following mnemonics MOV ADD LXI ADI 1 and 2 only2 and 3 only1, 2 and 3 only1, 2, 3 and 4 Loading... 16. Handshaking programmed data transfer is also known as Asynchronous transferSynchronous transferInterrupt driver transferBoth (a) and (c) Loading... 17. The addressing mode shown in the given figure is Immediate addressing modeDirect addressing modeRegister indirect addressing modeRegister addressing mode Loading... 18. Which of the following 8085 instructions affect all flags except the CY flag? ADC rINR rSEE MACI data Loading... 19. The addressing mode depicted in the given figure is Implicit addressing modeIndirect addressing modeRegister indirect addressing modeDirect addressing mode Loading... 20. The DW assembler directive in 8085 forces the assembler to initialize single or multiple data wordsforces the assembler to initialize a single data wordforces the assembler to initialize multiple consecutive bytes in the memory none of the above Loading... 21. Which of the following is not an assembler directive in 8085? DSDQDBEQU Loading... 22. The issue of a timing difference between a fast processor and slow memory is resolved by using a processor that's capable of waitingusing an external bufferusing a coprocessornone of these Loading... 23. Select the true statements Some microprocessors have only one type of address space.An address space is a set of all possible addresses which can be generated by a microprocessor.Two types of address spaces are memory and I/O address space.Each address in the address space allows a designer to provide at least one memory or I/O location in the system. Loading... 24. The integer range per word length in 8085 is -127 and 128-64 and 63-63 and 64-128 to 127 Loading... 25. What are the values of the control and status signals in an opcode fetch cycle that enable the memory buffer? Option IO/ S1 S0 Control Signal 1 1 1 0 =0 2 0 1 0 =0 3 0 0 1 =0 4 0 1 1 =0 1234 Loading... 26. If the instruction CMP B is executed while the contents of the accumulator are less than that of register B, then which flag will be set? Loading... 27. In 8085, the RST instruction will cause an interrupt _______. only if interrupts have been enabled by the EI (Enable interrupt) instructiononly if the interrupt mask bit is set to 0only if an ISR is not actively executingevery time it's executed Loading... 28. Which of the following are buses present in 8085? Address BusDMA busMemory BusControl Bus Loading... 29. On the execution of PUSH/POP instruction, the contents of the SP are incremented/decremented by 81621 Loading... 30. The values of odd and even parity flags are ___ and ___ respectively 0, 11, 00, 01, 1 Loading... 31. This is a type of interrupt where the external interrupting device supplies the address in addition to the interrupt request. Non-maskable interruptNon-vectored interruptMaskable interruptPolled interrupt Loading... 32. Which mode of Data Transfer Schemes (DTS) has the highest efficiency? Cycle stealing modeBurst modeNoneBoth Loading... 33. The content of the HL pair after the execution of the following instructions is ___. XRA A MOV L, A MOV H, L INX H DAD H 0000H0001H0011H0002H Loading... 34. To set a bit you can use ___ logic and to reset it you can use ___ logic. NOT, ANDOR, ANDAND, ORAND, NOT Loading... 35. A stack pointer stores the ____. Address of bottom of stackAddress of instruction being executedAddress of instruction to be executedAddress of top of stack Loading... 36. These commands in a program are not translated into machine instructions during assembly process: OperandsIdentifiersDirectivesMnemonics Loading... 37. The register which holds the information about the nature of results of arithmetic and logic operations is called as Condition code registerAccumulatorFlag registerProcess status register Loading... 38. An 8-bit microprocessor signifies that the processor has an 8-bit data bus8-interrupt lines8-bit controller8-bit address bus Loading... 39. Contents of opcode from memory are loaded into Instruction Register (IR) in this T-state: T1 opcodefetchT2 opcode fetchT3 opcode fetchT4 opcodefetch Loading... 40. What is the purpose of the READY signal in 8085 It's used to provide WAIT states when the 8085 is communicating with a slow peripheral deviceIt indicates that the 8085 is ready to receive inputsIt indicates that the 8085 is ready to provide Direct Memory AccessIt indicates that the 8085 is ready to send outputs Loading... 41. For memory mapped I/O, which of the following is true? Devices are accessed using IN and OUT instructionsDevices have 8-bit address lineThere can be maximum of 256 input devices and 256 output devicesArithmetic and logic operations can be directly performed with the I/O data Loading... 42. In I/O mapped I/O, which of the following is true? Devices have 16-bit address lineDevices are accessed using IN and OUT instructionsMemory map is shared between I/O and system memoryArithmetic and logic operations can be directly performed with the I/O data Loading... 43. RST0 - RST7 are the __________ in 8085. hardware interrupts logical interrupts software interrupts conditional interrupts Loading... 44. An 8-bit microprocessor can have ___ address lines. 81632Cannot be predicted Loading... 45. DMA refers to: direct memory access for the I/O devicedirect memory access for the external memorydirect memory access for microprocessornone of these Loading... 46. The Program Counter (PC) in a microprocessor is used to specify the address of the instruction to be executedspecify the address of the instruction currently executingspecify the number of instructions executednone of these Loading... 47. Upon the execution of the RET instruction: PC gets incrementedcontrol goes directly to the next instruction after the calling instruction without any operationcontrol goes directly to the next instruction after the calling instruction without any operation and also PC will get incrementedtop of the stack will get popped and get assigned to the PC Loading... 48. POP B is a 1 byte instruction2 byte instruction3 byte instruction4 byte instruction Loading... 49. Pick the instruction(s) that resets the accumulator SUB ACLR AORA AXRA A Loading... 50. The stack is a set of reserved I/O address spaceRAM address spaceROM address spaceCache address space Loading... 51. The frequency of the driving network connected between pins 1 and 2 of 8085 microprocessor is twice the desired frequencyfour times the desired frequencyeight times the desired clock frequencyequal to the desired frequency Loading... 52. If you wish to save the value of the accumulator on the stack, which of the following instruction will you use? PUSH PSWPUSH APOP PSWPUSH SP Loading... 53. S0 and S1 pins are used for latchcrystal oscillatorserial communicationindicating processor status Loading... 54. A high on RESET OUT indicates all the CPU registers are being resetall registers, counters and external chips are being resetprocessing can begin when this signal goes highnone of these Loading... 55. EQU memory directive stores ___ bytes in memory 12816 Loading... 56. Which of the following instructions have 6 T states? SPHLINXCALLRETXCHG Loading... 57. All jump/branch instructions in 8085 use ___________ addressing AbsoluteImmediateIndirectImplicit Loading... 58. Stack pointer is stored in RAMROMeither RAM/ROMMicroprocessor Loading... 59. Stack is stored in RAMROMEEPROMMicroprocessor Loading... 60. Which of the following is not true during the execution of an interrupt service routine, which does not contain any EI instructions the microprocessor can be interrupted by a non-mask able interrupt the microprocessor cannot be interrupted by any interruptthe microprocessor cannot be interrupted by any maskable interrupt all interrupts except non-maskable interrupt are disabled Loading... 61. The first operation performed in INTEL 8085 microprocessor after RESET is stack initializationprogram counter resetmemory read from the location 0000Hinstruction fetch from 0000H Loading... 62. After the execution of CMP A instruction ZF is set and CY is unchangedZF is reset and CY is setZF is set and CY is resetZF is reset and CY is unchanged Loading... 63. The 8085 microprocessor enters into bus idle machine cycle whenever RST 7.5 is recognizedINTR interrupt is recognizedDAD RP instruction is executednone of the above Loading... 64. The microprocessor issues ALE during first T-state of fetch cycle onlymemory READ cycle onlymemory WRITE cycle onlyevery machine cycle Loading... 65. The content of the A15-A8 (higher-order address lines) while executing “IN 8-bit port address” instruction are irrelevantall bits reset (i.e. 00H)all bits set (i.e. FFH)same as the content of A7-A0 Loading... 66. The execution of RST n instruction causes the stack pointer to increment by twodecrement by tworemain unaffectednone of the above Loading... 67. A sequence of two registers that multiplies the content of DE register pair by two and stores the result in HL register pair (in 8085 assembly language) is XCHG & DAD BXTHL & DAD HPCHL and DAD DXCHG and DAD H Loading... 68. Select the correct statement(s). In 8085, the data bus and the address bus are multiplexed in order to: Increase the speed of the microprocessorReduce the number of pinsConnect more peripheral chipsReduce power consumption Loading... 69. Both, the ALU and the control section of 8085 employs which special-purpose storage location? RegistersDecodersBuffersAccumulator Loading... 70. When we use a frequency counter for measuring frequency, two modes of measurement are preferred: Period mode and frequency mode. There is a certain value below which the period mode is preferred over frequency mode. Assuming that the oscillator frequency is 16MHz, what is the crossover frequency? 8KHz8MHz4KHz4MHz Loading... 71. The output data lines of microprocessor and memories are usually tristated because More than one device can transmit over the data bus at the same timeThe data line can be multiplexed for both input and outputIt increases the speed of data transfer over the data busMore than one device can transmit information over the data bus by enabling only one device at a time Loading... 72. A software breakpoint is a technique utilized during the debugging of the code. In this technique, breakpoints can be set at certain points in the code. When executed, the program stops execution at these breakpoints where the coder can look for register values and such. And then the execution can be carried forward from that particular breakpoint. Which feature of the 8085 allows for this technique? 16-bit registersDMAHardware interruptsSoftware interrupts Loading... 73. What will be the value in the memory location 7101H after the execution of the following code? The data at memory location 7100 is A7H. LXI H,7100H MOV A, M CMA INR A STA 7101H HLT 59H58H5AHnone of these Loading... 74. What will be the value in the memory location 7101H after the execution of the following code? The data at memory location 7100 is 35H. LDA 7100H ADD A ADD A STA 7101H HLT D4HD3H4DH3DH Loading... 75. SUB R and CMP R, both the instructions subtract the value stored in register R with the contents of the Accumulator and achieve the same result. TrueFalse Loading... 76. A programmer's model is ____. list of all I/O devices that can be connecteddiagrams of the internal bus architecturepart of the block diagram that a programmer can affect using the instruction setthe entire block diagram Loading... About The Writer Umair HussainiUmair has a Bachelors Degree in Electronics and Telecommunication.