More topics in 8085 Microprocessors Course

Interrupt Structure of the 8085

A microprocessor performs multiple tasks at a time – it accesses the memory, reads instructions, executes tasks, and performs so many more functions!

Amidst all these, there might be circumstances when there are unexpected tasks to be performed. These instructions might have some urgency to them. They might need access to the processor’s immediate attention. For instance, when a fighter plane detects a sudden intruder, it might want to alert the pilot to perform urgent defensive maneuvers.

Hence, there must be measures to handle such unpredictable situations. Because of this requirement, the 8085 and all processors are developed with an efficient interrupt handling system.

Different methods of Checking for Interrupts

Some interrupts can arise due to arithmetic operations, missing memory addresses, power fluctuations, or so on.

Many external devices are connected to the CPU-  for example,  a mouse, keyboard, printer, scanner, joystick, etc. For these devices to operate, they require the CPU’s attention.  The CPU also needs to respond to the input from these I/O devices.

If multiple I/O devices are connected, how do we check which device is raising an interrupt and asking for the CPU’s immediate attention?

There are different ways of checking for interrupts in the processor – namely, Polling and Interrupt. We shall discuss these approaches here.

Polling

On a bright Sunday morning, you are sitting on a couch waiting for your friend to arrive. You don’t know what time they would reach, but you keep going to your door, checking through the peephole every five minutes to see if your friend has arrived. Finally, when you check after a few times, you notice your friend approaching, and you open the door to welcome them. This is somewhat similar to the process of Polling.

  • In Polling, the processor continuously checks whether any external I/O device that has been connected to the system requires special attention.
  • This external device informs the processor if it needs servicing.
  • Once this device informs the processor about the required service, the system pauses its current execution and shifts to processing the device.
  • This request is raised by updating the status register or the command ready bit of the device with the required signal.
  • When the microprocessor reads this command ready bit as a ‘1’, it means the device requires attention and has some commands to be executed. If it is set to ‘0’, then no servicing is needed.

Polling is not described as a hardware mechanism but is instead a protocol used. Once the external device informs about its readiness for working, the processor immediately sets on working for it, instead of any other component.

The only disadvantage with Polling is that the microprocessor needs to continually check the external devices attached and see if it needs any processing to be done. Thus, this wastes a lot of time of the processor and delays every other pending task to be carried out.

But the question now is – what if there are multiple I/O devices connected to the Intel 8085? What would be the criteria and method for Polling in such circumstances?

In such cases, the round-robin approach is implemented. The processor asks every device one by one in a circular fashion, checking if any device requires the execution of respective instructions. Once all the devices have been checked, the entire loop begins again, with each device being monitored again individually, one at a time in the same sequence.

Interrupt

Let us see how Interrupt is different from Polling with the help of the same previous example.

You are expecting a friend at your residence on a bright Sunday morning, totally unaware of their time of arrival. So you go ahead with your everyday tasks, making breakfast for yourself, watching the TV, and enjoying the cool air. Suddenly, you hear the doorbell ring. You peep through the door hole to see your friend and welcome them inside. This doorbell ring can be considered as an interrupt.

  • In interrupts, the onus of informing the processor is on the device that requires the processor’s attention.
  • An interrupt is more of a hardware mechanism in microprocessors.
  • Any hardware device which needs attention throws an interrupt by notifying the processor.
  • The CPU need not continually check the status of the hardware, and thus this method saves the CPU cycles, hence taking lesser time than the Polling mechanism.
  • When servicing is to be done, it is managed by the Interrupt Handler. The indication of servicing for the device is done by sending a signal on the interrupt request line.

When the processor senses an incoming signal on the interrupt request line, it stops its current execution and responds to the interrupt raised by the I/O device – this is done by passing the execution control to the interrupt handler. The interrupt handler (also called the Interrupt Service Routine) then resolves this thrown interrupt by servicing the device.

Once the interrupt handler completes handling the execution of the interrupt, the processor resumes the previous task, which had been paused.

This interrupt need not be thrown by a hardware element alone. It can also be any software issue, user problem, or some error in the execution of normal functioning. This interrupt managing nature of the processor leads to multitasking, where the user can perform multiple tasks at the same time.

If the processor receives more than one interrupt request, the ISR gets triggered. Thus, it begins prioritizing the interrupts which are waiting to be processed and arranges them in an ordered queue to receive servicing.

Microprocessor’s Response to an Interrupt

The microprocessor has about a million instructions to execute per cycle. When the 8085 is executing the programs, it keeps a constant check on the interrupt lines after each instruction. If any interrupt line is appeared to be ‘enabled,’ it first completes the execution of the ongoing instruction. If there are multiple interrupt lines ‘enabled,’ then the one with the higher priority is served first.

  • Once the current instruction has been executed, the processor saves the address of the next instruction in line (the program counter value) onto the stack and attends the interrupt.
  • Each interrupt is assigned with a vectored address in the memory. In simple words, every vectored interrupt knows exactly where it has to go in the memory to get itself serviced.
  • This memory location holds the instruction which solves the interrupt.
  • Thus, when the microprocessor attends the interrupt, it gets this address, and the program control shifts to this address.
  • It then attends the interrupt and serves the service routine on this location. At the end of the service routine is the RET instruction. Upon reaching this return (RET) instruction, the processor pops out the address of the previously saved instruction from the stack and continues executing the normal program instructions.

Classification of Interrupts

Interrupts are classified in two ways:

  • Maskable and Non-Maskable Interrupts 
  • Vectored and Non-Vectored Interrupts
  • Hardware and Software Interrupts

Maskable Interrupts

Maskable interrupts are those interrupts that can be delayed or denied. Any interrupt which can be disabled by giving appropriate instructions is termed as maskable interrupts. Masking prevents the interrupt from disturbing the main program execution. Very useful in cases of interrupts that are low priority and don’t need to disturb the original program.

Non-Maskable Interrupts

These interrupts cannot be disabled using any instructions. The TRAP interrupt is one of the non-maskable interrupts. It is used in critical power failure situations.

Vectored Interrupts

Vectored Interrupts have fixed vector addresses, which is the starting address of the sub-routine. Once the microprocessor encounters this, it jumps to the sub-routine and executes the instructions. After executing these, the program control shifts back to the normal program’s instruction address and continues running.

Non-Vectored Interrupts

Non-Vectored Interrupts are those that do not have a predefined vector address. The INTR interrupt is the only non-vectored interrupt in the Intel 8085 microprocessor.

Hardware Interrupts

The hardware interrupts in the 8085 are initiated (or raised) by an external device by applying an appropriate signal at the interrupt pin of the microprocessor. If the interrupt gets accepted, the processor attends the request and executes the respective interrupt service routine (ISR). The Intel 8085 are five distinct interrupt pins  (pins 6 to 10 in the Pin Diagram) which are used as the Hardware Interrupts:

    1. TRAP
    2. RST 7.5
    3. RST 6.5
    4. RST 5.5
    5. INTR
8085 Pin Diagram
8085 Pin Diagram

The Vector Addresses of these interrupts are listed below:

Interrupt Vector Address
RST7.5 003CH
RST6.5 0034H
RST5.5 002CH
TRAP 0024H

Let us learn about each of these interrupts in detail.

TRAP

The TRAP is a non-maskable, edge & level-triggered processor interrupt. It has the highest priority compared to all the other interrupts. This interrupt can only be masked by resetting the processor itself. Else it cannot be ignored. Instead, it can be delayed a bit using the HOLD signal. Upon attending the request, the interrupt transfers the program control to the location 0024H, which holds the instructions for servicing it.

Edge & level-triggered interrupt means that once the TRAP interrupt is raised a.k.a goes high, it remains high until it is serviced/acknowledged. In case there is any unexpected power failure, it executes an ISR and then sends the data from the Main Memory to the Backup Memory.

RST 7.5

This is the second-highest priority interrupt. It is a maskable one and an edge-sensitive interrupt. The vector address of RST 7.5 is 003CH. Like the TRAP, this interrupt can also be reset or masked by resetting the processor itself. You can also reset in using the DI instruction.

RST 6.5 and RST 5.5

These two are level-triggered, and maskable processor interrupts. When the RST 6.5 pin is at logic 1 (set to high), the IE flip-flop is then set. The RST 6.5 has the third-highest priority, followed by the RST 5.5 having the fourth highest. These can be masked by using the DI and SIM instructions, or by simply resetting the microprocessor.

INTR

It is, again, a level- triggered & maskable interrupt. It holds the least priority and can be disabled by using the DI or SIM instruction or simply resetting the 8085.

Software Interrupts

The software interrupts are interrupt instructions that pop up during the program execution. These instructions are placed at desired locations in between a program. Thus, while the program is running, if such software interrupts are encountered, the 8085 executes the respective interrupt service routine for that interrupt. These software interrupts cannot be masked or disabled.

The Intel 8085 has eight software interrupts

    1. RST 0
    2. RST 1
    3. RST 2
    4. RST 3
    5. RST 4
    6. RST 5
    7. RST 6 and
    8. RST 7.

The Vector Addresses of these eight interrupts are listed below:

Interrupt Vector Address
RST 0 0000H
RST 1 0008H
RST 2 0010H
RST 3 0018H
RST 4 0020H
RST 5 0028H
RST 6 0030H
RST 7 0038H

There is also another method of calculating the vector addresses :

Interrupt value * 8 = X

Convert X to its equivalent hexadecimal value. This will give you the respective Vector Address.

Let us see an example of this. Consider the Interrupt RST 5.

X=5 * 8 = 40, which equals to 28H

Interrupt Priorities

When the 8085 microprocessor receives multiple interrupt requests at the same time, it will attend and execute the interrupt service routine (ISR) according to the priority levels of these interrupts.

The TRAP has the highest interrupt, and the INTR has the least.

Interrupt Priorities
Interrupt Priorities

Working of Vectored Interrupts

We know that Vectored Interrupts have fixed addresses for the interrupts. Let us understand the Non-Vectored Interrupt process as a series of steps.

  1. To begin with, interrupt processing should be enabled in 8085 using EI instruction. This will be explained in the upcoming topics.
  2. After the execution of each instruction, the processor checks if there is an interrupt request.
  3. If the 8085 sees an interrupt, it first completes the execution of the current instruction.
  4. The 8085 then saves the next instruction’s memory location onto the processor stack.
  5. The processor meets the interrupt request, which indicates the vector address of the ISR.
  6. The program control is then shifted to the ISR call location specified by the interrupt by the CALL instruction.
  7. The microprocessor then performs the ISR.
  8. At the end of the ISR, the processor comes across the RET instruction. The microprocessor then returns back and retrieves the address stored on its stack.
  9. The program then continues normal execution.

Working of Non-Vectored Interrupts

We have already been introduced to Vectored Interrupts. INTR is the only non-vectored interrupt in the 8085 system. Let us understand the Non-Vectored Interrupt process as a series of steps.

  1. First and foremost, the interrupt process should be enabled in the system using the EI instruction.
  2. At the end of every instruction, the 8085 checks for an interrupt between the execution.
  3. If the INTR signal is high, the microprocessor completes the execution of the current instruction, disables the interrupt, and then sends the INTA signal (Interrupt Acknowledgement) to the device, which has raised the interrupt.
  4. The INTA permits the interrupting I/O device to send an RST instruction through the data bus. There are eight number of locations for the INTR interrupt. These locations are nothing, but the software interrupts RST0-RST7.
  5. Once the INTA signal has been received,  the 8085 saves the next instruction’s memory location onto the stack.
  6. The program is then transferred to the ISR call location specified by the RST instruction.
  7. The microprocessor then goes ahead and performs the ISR. This ISR must include the EI instruction to enable any further interrupts in the program.
  8. At the end of the ISR, the processor read the RET instruction. This allows the microprocessor to return back and retrieve the address stored on the stack.
  9. The program then continues normal execution.

Enabling of Interrupts

Inside the Intel 8085, there is a flip-flop called the IE flip-flop. Here, IE stands for Interrupt Enable. When this flip-flop is reset to the 0 state, the 8085 interrupt system gets disabled. That is, even if there is a situation where an external interrupt pin gets activated, the corresponding interrupt signal isn’t activated. The internal architecture of the Intel 8085 interrupt structure is shown below.

Interrupt Architecture of 8085
Interrupt Architecture of 8085

From the architecture, we see that the IE flip-flop state has no control over the internal interrupt signal corresponding to the TRAP interrupt. As mentioned earlier, the TRAP is the highest priority interrupt, which cannot be masked. Thus, whenever the external TRAP pin gets activated, the corresponding interrupt signal is activated.

The interrupt process is enabled by using the EI instruction in the processor’s instruction execution. The EI is a 1-byte instruction that enables the interrupt process. Enabling interrupts will allow the processor to save the current instruction in the stack and jump to the interrupt service routine. Once the interrupt has been attended, the program control returns to the normal program.

Disabling of Interrupts

Apart from the TRAP interrupt, the interrupt system can be disabled by managing the IE flip-flop. The IE flip-flop is reset to 0 state by the given conditions –

  • Execution of the DI instruction
  • Recognizing an interrupt request;
  • Resetting of the Intel 8085

The DI instruction in 8085 stands for “Disable Interrupts.” DI is a 1-Byte instruction which resets the IE flip-flop when executed. This disables the entire 8085 interrupt system except for the TRAP pin.

Once the 8085 recognizes an interrupt raised, it executes its ISR. Without a doubt, the processor would not like being interrupted again amidst executing the ISR. Thus, the 8085 will place itself under the DI state once an interrupt is recognized. Nonetheless, the TRAP interrupt can still interrupt an ongoing ISR. There is no necessity to specify the DI instruction at the beginning of an ISR. It is disabled by default.

Set Interrupt Mask (SIM)

The Intel 8085 provides an additional facility for masking for the interrupts RST 7.5, RST 6.5 and RST 5.5. The Set Interrupt Mask (SIM) is used to implement the 8085 hardware interrupts (RST 7.5, RST 6.5, RST 5.5). This is carried out by setting certain bits to form ‘masks’ or by generating output data through the Serial Output Data (SOD) line. The required mask value is first loaded in the accumulator register – the SIM will then take the bit pattern from it. The status of the interrupts can be read by running the RIM instruction.

Set Interrupt Mask
Set Interrupt Mask

Read Interrupt Mask (RIM)

The status of all pending interrupts can be read by using the Read Interrupt Mask (RIM) instruction. RIM performs the following tasks:

  • Reads the interrupt mask (bit 2, bit 1, bit 0)
  • Identify the pending interrupts (bit 6, bit 5, bit 4)
  • Receive the Serial Input Data bit (bit 7)

When the RIM instruction gets executed, a byte of information is loaded into the accumulator, which can be accurately interpreted as given below.

Read Interrupt Mask
Read Interrupt Mask

We hope that you are now able to understand the entire process of how interrupts work, their classification, types, and internal circuitry. Interrupts are a very important topic of this 8085 microprocessor course and beyond. Almost every modern processor has this feature built-in, and thus it’s necessary to be thorough with the concept. If you have any doubts, let us know in the comments section below.

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