A Comparator is a combinational circuit that gives output in terms of A>B, A<B, and A=B. This is entirely expected from the name. A digital comparator’s purpose is to compare numbers and represent their relationship with each other.

In this post, we will make different types of comparators using digital logic gates. We will begin by designing a simple 1-bit and * 2-bit* comparators. The circuit for a

*will get slightly more complex. Let’s begin.*

**4-bit comparator****How to design a simple 1-bit comparator?**

A 1-bit comparator compares two single bits.

A |
B |
A>B |
A<B |
A=B |

0 | 0 | 0 | 0 | 1 |

0 | 1 | 0 | 1 | 0 |

1 | 0 | 1 | 0 | 0 |

1 | 1 | 0 | 0 | 1 |

Let’s apply a shortcut to find the equations for each of the cases. Normally, we can use a K-map. But this shortcut is efficient and handy when you understand it.

For A>B, there is only one case when the output is high when A=1 *and* B=0. Let’s call this X. We can write the equation as follows

X(which stands for A>B) = AB’

Similarly, denote A<B with Y and A=B with Z.

Since Y is high when A=0 and B=1, we get the following equation

Y = A’B

Since Z is high in two cases, there will be an OR gate. This is because the logic behind an OR gate is that a high output can be achieved in one or more cases. Z is high when A=0 and B=0, it is also high when A=1 and B=1. Therefore,

Z = A’B’ + AB

This is similar to the equation of an EXNOR gate. Hence,

Z = AB

**How to design a 2-bit comparator?**

Let’s plot the truth table for a 2-bit comparator

A1 |
A0 |
B1 |
B0 |
A>B |
A<B |
A=B |

0 | 0 | 0 | 0 | 0 | 0 | 1 |

0 | 0 | 0 | 1 | 0 | 1 | 0 |

0 | 0 | 1 | 0 | 0 | 1 | 0 |

0 | 0 | 1 | 1 | 0 | 1 | 0 |

0 | 1 | 0 | 0 | 1 | 0 | 0 |

0 | 1 | 0 | 1 | 0 | 0 | 1 |

0 | 1 | 1 | 0 | 0 | 1 | 0 |

0 | 1 | 1 | 1 | 0 | 1 | 0 |

1 | 0 | 0 | 0 | 1 | 0 | 0 |

1 | 0 | 0 | 1 | 1 | 0 | 0 |

1 | 0 | 1 | 0 | 0 | 0 | 1 |

1 | 0 | 1 | 1 | 0 | 1 | 0 |

1 | 1 | 0 | 0 | 1 | 0 | 0 |

1 | 1 | 0 | 1 | 1 | 0 | 0 |

1 | 1 | 1 | 0 | 1 | 0 | 0 |

1 | 1 | 1 | 1 | 0 | 0 | 1 |

The shortcut that we saw above can be used here too. But notice that since we have four variables (A1, A0, B1, B0) and each of the three outputs is high at least four times, the equations that we will get will have four terms of 4 variables. At least. So, though applying the shortcut is possible, we won’t.

K-maps come in handy in situations like these. Because it is possible to achieve the most straightforward equation using them, and remember, the simpler the equation, the lesser the logic gates required. That is the aim of any designing process – to obtain the simplest hardware implementation.

Using K-maps

we get the following equations

A>B = A1B1′ + B0′(A0B1′ + A0A1)

A<B = B1A1′ + B0B1A0′ + A1’A0’B0

A=B = .

**How to design a 4**–**bit comparator?**

The truth table for a 4-bit comparator would have 4^4 = 256 rows. So we will do things a bit differently here. We will compare each bit of the two 4-bit numbers, and based on that comparison and the weight of their positions, we will draft a truth table.

A3B3 |
A2B2 |
A1B1 |
A0B0 |
A>B |
A<B |
A=B |

A3>B3 | x | x | x | 1 | 0 | 0 |

A3<B3 | x | x | x | 0 | 1 | 0 |

A3=B3 | A2>B2 | x | x | 1 | 0 | 0 |

A3=B3 | A2<B2 | x | x | 0 | 1 | 0 |

A3=B3 | A2=B2 | A1>B1 | x | 1 | 0 | 0 |

A3=B3 | A2=B2 | A1<B1 | x | 0 | 1 | 0 |

A3=B3 | A2=B2 | A1=B1 | A0>B0 | 1 | 0 | 0 |

A3=B3 | A2=B2 | A1=B1 | A0<B0 | 0 | 1 | 0 |

A3=B3 | A2=B2 | A1=B1 | A0<B0 | 0 | 0 | 1 |

Now let’s derive the equations for the three outputs.

**A=B**

Recall the 1-bit comparator circuit we saw above. The equation for the A=B condition was AB. Let’s call this x. Taking a look at the truth table above, A=B is true only when A3=B3 and A2=B2 and A1=B1 and A0=B0. Hence

Z (A=B) = A3B3 . A2B2 . A1.B1 . A0.B0 = x3x2x1x0

**A>B**

Since there are multiple occasions where this particular condition is high, we will OR (add) each of those individual occasions. We find the first instance of A>B at the top of the table where A3>B3. For this to be possible in a binary system, A3 has to be equal to 1, and B3 has to be equal to 0. Since there are only 0s and 1s in a binary system. We can represent this as A3.B3′. Moving on to the next instance of A>B, we can see that it occurs at A3=B3 *and* A2>B2. From the equation for A=B above, A3=B3 can be represented as x3. And this entire instance can be written as x3A2B2′. Similarly, deriving equations for the remaining instances, we get the following equation

X(A>B) = A3B3′ + x3A2B2′ + x3x2A1B1′ + x3x2x1A0B0′

**A<B**

Employing the same principles we used above, we get the following equation

Y(A<B) = A3’B3 + X3A2’B2 + X3X2A1’B1 + X3X2X1A0’B0

Designing the circuit based on the above equations, we get the following logic diagram for a 4-bit comparator.

**How do I remember this? **

This is the exact question I had when I first studied this truth table. I felt that this truth table was made only because whoever made it knew that it had to be made this way. How would I, as a student, be expected to devise a new system for a truth table? The answer is, you don’t have to. You are entirely free to do it the old way with 256 rows. But this is a more natural way to deal with when you have many variables that will end up in a vast truth table. You can remember it and maybe use it elsewhere when the need arises. If not, that’s okay, too; you can bookmark this page and refer to it when you are tasked with making a huge truth table.

*Note: *

*This post is a part of our free course on Digital Electronics and Digital Logic Design.**We will use all of the equations above when we code these comparators in our VHDL and Verilog course.*

thanks bro

Glad to help!